Multilayer substrate for semiconductor packaging

Patent metadata

Field	Value
Publication number	US-9788416-B2
Application number	US-201414778987-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 22, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A multilayer substrate for semiconductor packaging, comprising:
a first layer with a first side and a second side opposite the first side, wherein the first side has a first side xy-plane defined by three highest points on the first side, and individual locations on the first side have a first side distance between the first side xy-plane and the first side below the first side xy-plane in a direction towards the second side, wherein the second side has a second side xy-plane defined by three highest points on the second side, and individual locations on the second side have a second side distance between the second side xy-plane and the second side below the second side xy-plane in a direction towards the first side; and
a second layer comprised of one or more layers of one or more dielectric materials, the second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at individual locations on the second layer is comprised of the first side distance plus the second side distance, wherein a thickness of the first layer plus the thickness of the second layer at individual locations between the first side of the first layer and the second side of the second layer is a substantially uniform thickness.

2. The substrate of claim 1 , wherein the first layer has electrical routing features to route electrical signals between the first side of the first layer and the second side of the first layer, wherein the second layer has electrical routing vias electrically coupled to the electrical routing features of the second side of the first layer and passing through the second layer from the first side of the second layer to the second side of the second layer, wherein the electrical routing vias have a depth corresponding to the thickness of the second layer.

3. The substrate of claim 1 , wherein the dielectric materials are selected from a group consisting of Ajinomoto Build-up Film (ABF), fire retardant 2 material (FR2), fire retardant 4 material (FR4), polyimide, passivation film (WPR), poly benzthiazole (PBZT), poly benzoxazole (PBO), and mold compound, and combinations thereof.

4. The substrate of claim 1 , wherein the thickness of the second layer at the individual locations on the second layer is comprised of the first side distance plus the second side distance plus an offset distance, wherein the offset distance is less than approximately two times a sum of the first side distance and the second side distance.

5. The substrate of claim 1 , wherein the first layer is a multilayer composite substrate with a core.

6. A method of making a multilayer substrate for semiconductor packaging, the method comprising:
providing a first layer with a first side and a second side opposite the first side, wherein the first layer is unconstrained, wherein the first side has a first side xy-plane defined by three highest points on the first side, and individual locations on the first side have a first side distance between the first side xy-plane and the first side below the first side xy-plane in a direction towards the second side, wherein the second side has a second side xy-plane defined by three highest points on the second side, and individual locations on the second side have a second side distance between the second side xy-plane and the second side below the second side xy-plane in a direction towards the first side;
constraining the first layer by flattening the first side of the first layer against a surface of a rigid vacuum plate to provide a constrained first layer, wherein the second side of the first layer has a constrained second side distance that is a sum of the first side distance and the second side distance; and
coupling a second layer to the constrained first layer, the second layer comprised of one or more layers of one or more dielectric materials, the second layer with a first side coupled to the second side of the first layer and with a second side opposite the first side of the second layer, wherein a thickness of the second layer at individual locations on the second layer is comprised of the constrained second side distance, wherein a thickness of the first layer plus the thickness of the second layer at individual locations between the first side of the first layer and the second side of the second layer is a substantially uniform thickness.

7. The method of claim 6 , wherein the coupling of the second layer to the first layer further comprises:
laminating, coating, or casting one or more layers of one or more dielectric materials.

8. The method of claim 7 , wherein the coupling of the second layer to the first layer comprises laminating, wherein the laminating further comprises:
sequentially attaching, conformally pressing, and plate pressing three build-up layers.

9. The method of claim 6 , further comprising:
removing the rigid vacuum plate from the first side of the first layer to provide an unconstrained multilayer substrate.

10. A semiconductor package, comprising:
a die; and
substrate with the die mounted in a flip chip configuration on the substrate, the substrate further comprising:
a first layer that is a multilayer composite substrate with a core, the first layer with a first side and a second side opposite the first side, the die coupled to the first side of the first layer,
wherein before the die is coupled to the first side of the first layer, the first side has a first side xy-plane defined by three highest points on the first side, and individual locations on the first side have a first side distance between the first side xy-plane and the first side below the first side xy-plane in a direction towards the second side,
wherein before the die is coupled to the first side of the first layer, the second side has a second side xy-plane defined by three highest points on the second side, and individual locations on the second side have a second side distance between the second side xy-plane and the second side below the second side xy-plane in a direction towards the first side; and
a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer,
wherein a thickness of the second layer at individual locations on the second layer is comprised of the first side distance plus the second side distance,
wherein a thickness of the first layer plus the thickness of the second layer at individual locations between the first side of the first layer and the second side of the second layer is a substantially uniform thickness.

11. The package of claim 10 , wherein the first layer has electrical routing features to route electrical signals between the first side of the first layer and the second side of the first layer, wherein the second layer has electrical routing vias electrically coupled to the electrical routing features of the second side of the first layer and passing through the second layer from the first side of the second layer to the second side of the second layer, wherein the electrical routing vias have a depth corresponding to the thickness of the second layer.

12. The package of claim 10 , wherein the second layer is comprised of one or more layers of one or more dielectric materials.

13. The package of claim 12 , wherein the dielectric materials are selected from a group consisting of Ajinomoto Build-up Film (ABF), fire retardant 2 material (FR2), fire retardant 4 material (FR4), polyimide, passivation film (WPR), poly benzthiazole (PBZT), poly benzoxazole (PBO), and mold compound, and combinations thereof.

Assignees

• Intel Corp

Inventors

• Jen Wei-Lun Kane
• Jain Padam
• Seneviratne Dilan
• Chen Chi-Mon

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P90/18

  by shaping · CPC title

• H10P90/12

  Preparing bulk and homogeneous wafers · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title