Power saving control apparatus and method

Patent metadata

Field	Value
Publication number	US-9787716-B2
Application number	US-26952308-A
Country	US
Kind code	B2
Filing date	Nov 12, 2008
Priority date	Nov 16, 2007
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A power-saving control apparatus includes a memory storing first to Nth different authentication codes, determines, every time a signal including an authentication code is received, whether the authentication code in the received signal is a valid code which matches one of the authentication codes in the memory, outputs an operation signal to a main apparatus when the authentication code in the received signal is determined to be the valid code, and generates a new authentication code, when (a) the number of times the authentication code in each received signal matches a first authentication code of the authentication codes in the memory is equal to a predetermined value or (b) the authentication code in the received signal matches a second or subsequent authentication code of the authentication codes in the memory, to delete one of the authentication codes in the memory, and to store the new authentication code in the memory.

First claim

What is claimed is:

1. A power-saving control apparatus comprising:
a first memory to store first to Nth (N is a natural number not less than two) different first authentication codes;
a second memory to store first to Mth (M is a natural number not less than two) different second authentication codes;
a reception circuit to receive (a) a first radio operation signal including a first authentication code and a second authentication code or (b) a second radio operation signal including the first authentication code and a third radio operation signal including the second authentication code, the first authentication code being included in the first authentication codes, the second authentication code being included in the second authentication codes;
a first determination circuit to determine, every time the reception circuit receives the first radio operation signal or both the second radio operation signals and the third radio operation signal, whether the first authentication code in the first radio operation signal or the second radio operation signal is a first valid code which matches one of the first authentication codes stored in the first memory;
a second determination circuit to be started when the first determination circuit determines that the first authentication code in the first radio operation signal or the second radio operation signal is the first valid code, and to determine whether the second authentication code in the first radio operation signal or the third radio operation signal received is a second valid code which matches one of the second authentication codes stored in the second memory;
an output circuit to output an operation signal to a main apparatus when the second determination circuit determines that the second authentication code in the first radio operation signal or the third radio operation signal is the second valid code;
a first control circuit to generate a new second authentication code, every time the second determination circuit determines that the second authentication code in the first radio operation signal or the third radio operation signal received is the second valid code, to delete at least one of the second authentication codes stored in the second memory, the at least one of the second authentication codes being the second valid code, and to store the new second authentication code in the second memory;
a counter circuit to count the number of times the first authentication code in the first radio operation signal or the second radio operation signal received matches a first one of the first authentication codes stored in the first memory; and
a second control circuit to generate a new first authentication code, when (a) a value of the counter circuit is equal to a predetermined set value or (b) the first authentication code in the first radio operation signal or the second radio operation signal matches a second or subsequent one of the first authentication codes stored in the first memory, to delete at least one of the first authentication codes stored in the first memory, and to store the new first authentication code in the first memory,
wherein when a replay attack is taken, the first determination circuit determines that the first authentication code in the first radio operation signal or the second radio operation signal received is the first valid code and the second determination circuit determines that the second authentication code in the first radio operation signal or the third radio operation signal received is an invalid code which is not included in the second authentication codes stored in the second memory.

2. The apparatus according to claim 1 , wherein the second control circuit generates the new first authentication code, when the first determination circuit determines that the first authentication code in the first radio operation signal or the second radio operation signal received is the first valid code and the second determination circuit determines that the second authentication code in the first radio operation signal or the third radio operation signal received is an invalid code which is not included in the second authentication codes stored in the second memory, to delete at least one of the first authentication codes stored in the first memory, and to store the new first authentication code in the first memory.

3. The apparatus according to claim 1 , wherein the second control circuit deletes the first one of the first authentication codes from the first memory.

4. A power-saving control apparatus comprising:
a first memory to store first to Nth (N is a natural number not less than two) different first authentication codes;
a second memory to store first to Mth (M is a natural number not less than two) different second authentication codes;
a reception circuit to receive (a) a first radio operation signal including a first authentication code and a second authentication code or (b) a second radio operation signal including the first authentication code and a third radio operation signal including the second authentication code, the first authentication code being included in the first authentication codes, the second authentication code being included in the second authentication codes;
a first determination circuit to determine, every time the reception circuit receives the first radio operation signal or both the second radio operation signals and the third radio operation signal, whether the first authentication code in the first radio operation signal or the second radio operation signal is a first valid code which matches one of the first authentication codes stored in the first memory;
a second determination circuit to be started when the first determination circuit determines that the first authentication code in the first radio operation signal or the second radio operation signal is the first valid code, and to determine whether the second authentication code in the first radio operation signal or the third radio operation signal received is a second valid code which matches one of the second authentication codes stored in the second memory;
an output circuit to output an operation signal to a main apparatus when the second determination circuit determines that the second authentication code in the first radio operation signal or the third radio operation signal is the second valid code;
a first control circuit to generate a new second authentication code, every time the second determination circuit determines that the second authentication code in the first radio operation signal or the third radio operation signal received is the second valid code, to delete at least one of the second authentication codes stored in the second memory, the at least one of the second authentication codes being the second valid code, and to store the new second authentication code in the second memory;
a counter circuit to count the number of times the first authentication code in the first radio operation signal or the second radio operation signal received matches a first one of the first authentication codes stored in the first memory; and
a second control circuit to generate a new first authentication code, when (a) a value of the counter circuit is equal to a predetermined set value or (b) the first authentication code in the first radio operation signal or the second radio operation signal matches a second or subsequent one of the first authentication codes stored in the first memory, to delete at least one of the first authentication codes stored in the first memory, and to store the new first authentication code in the first memory;
wherein when a replay attack is taken, the first determination circuit determines that the first authentication code in the first radio operation signal or the second radio operation signal received is the first valid code an

Assignees

• Mera Keisuke
• Doi Yusuke
• Sakamoto Takafumi
• Umeda Toshiyuki
• Otaka Shoji
• Toshiba Kk

Inventors

• Mera Keisuke
• Doi Yusuke
• Sakamoto Takafumi
• Umeda Toshiyuki
• Otaka Shoji

Classifications

• H04W12/06

  Authentication · CPC title

• H04W52/0229

  where the received signal is a wanted signal · CPC title

• H04L63/08

  for authentication of entities (cryptographic mechanisms or cryptographic arrangements for entity authentication H04L9/32) · CPC title

• H04L63/166 Primary

  at the transport layer · CPC title

• Y02B60/50

  Cross-Sectional Technologies · mapped topic