Multi-rate transmissions over twinax cables

Patent metadata

Field	Value
Publication number	US-9787519-B2
Application number	US-201414466327-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Aug 23, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

First claim

What is claimed is:

1. A cable assembly, comprising:
four or less twin axial cables configured for communicating signals in opposite directions;
a plug assembly configured for associating one end of the four or less twin axial cables with an interconnect, and connecting another end with an interface port, wherein the plug assembly comprising:
a transceiver configured for communicating the signals, respectively, in the opposite directions to and from the interface port, wherein the transceiver transmits a first signal of the signals at a first transmission rate and simultaneously transmits a second signal of the signals at a second transmission rate via the four or less twin axial cables, and wherein the second transmission rate is different from the first transmission rate; and
a processor operatively coupled to the transceiver that is configured for digital signal processing of the signals via the four or less twin axial cables, the processor being integrated on a head of a twin axial cable of the four or less twin axial cables and connected to the interconnect to facilitate connecting the twin axial cable to the interconnect, the interconnect facilitating connecting the twin axial cable and the processor with a circuit board associated with the interconnect.

2. The cable assembly of claim 1 , wherein the four or less twin axial cables are configured to comprise a set of conductors comprising not more than eight conductors, the not more than eight conductors being configured for communicating the signals at a speed of at least one hundred gigabytes per second.

3. The cable assembly of claim 2 , wherein the four or less twin axial cables comprise a single, full duplex twin axial cable.

4. The cable assembly of claim 1 , wherein the first transmission rate is at least forty gigabytes per second and is associated with a first twin axial cable of the four or less twin axial cables, and the second transmission rate is at least ten gigabytes per second and is associated with a second twin axial cable of the four or less twin axial cables.

5. The cable assembly of claim 4 , wherein the four or less twin axial cables comprise a third twin axial cable configured for communicating a third signal at a third transmission rate of at least forty gigabytes per second and a fourth twin axial cable configured for communicating a fourth signal at a fourth transmission rate of at least ten gigabytes per second.

6. The cable assembly of claim 1 , wherein the processor is configured to transmit the signals at different transmission rates simultaneously via the four or less twin axial cables with a surface mount assembly that is coupled to the transceiver.

7. The cable assembly of claim 1 , wherein the four or less twin axial cables are configured to transmit the signals in the opposite directions at different transmission rates by encoding the signals in a first communication protocol based on the first transmission rate and a second communication protocol based on the second transmission rate.

8. The cable assembly of claim 1 , wherein the four or less twin axial cables are configured to transmit the signals at a speed of at least one hundred fifty gigabytes per second, and the processor is communicably integrated to the plug assembly via connections from a processor package mount.

9. A signal processing method comprising:
receiving signals from four or less twin axial cables via a plug assembly comprising a processor and a transceiver;
encoding, by the processor, the signals with communication protocols to generate encoded signals; and
concurrently transmitting, by the transceiver, a first encoded signal of the encoded signals at a first transmission rate and a second encoded signal of the encoded signals at a second transmission rate that is different from the first transmission rate via separate twin axial cables of the four or less twin axial cables, the processor being integrated on a head of a first twin axial cable of the four or less twin axial cables and connected to an interconnect to facilitate connecting the first twin axial cable to the interconnect, the interconnect facilitating connecting the first twin axial cable and the processor with a circuit board associated with the interconnect and the transceiver.

10. The method of claim 9 , wherein the first transmission rate is at least one hundred gigabytes per second.

11. The method of claim 9 , wherein the concurrently transmitting the first encoded signal at the first transmission rate and the second encoded signal at the second transmission rate comprises concurrently communicating the first encoded signal via the first twin axial cable at a speed of at least forty gigabytes per second and communicating the second encoded signal via a second twin axial cable of the four or less twin axial cables at a speed of at least ten gigabytes per second.

12. The method of claim 9 , wherein the concurrently transmitting the first encoded signal at the first transmission rate and the second encoded signal at the second transmission rate comprises concurrently transmitting the first encoded signal at the first transmission rate via the first twin axial cable and the second encoded signal at the second transmission rate via a second twin axial cable of the four or less twin axial cables, the first transmission rate and the second transmission rate respectively being at least forty gigabytes per second, and wherein the method further comprises:
communicating a third encoded signal of the encoded signals via a third twin axial cable of the four or less twin axial cables and a fourth encoded signal of the encoded signals via a fourth twin axial cable of the four or less twin axial cables at respective transmission rates of at least ten gigabytes per second.

13. The method of claim 9 , further comprising:
encoding a first signal in a first communication protocol to facilitate transmitting the first encoded signal at the first transmission rate via the first twin axial cable and a second signal in a second communication protocol to facilitate simultaneously transmitting the second encoded signal at the second transmission rate via a second twin axial cable of the four or less twin axial cables.

14. The method of claim 9 , further comprising:
determining, by the processor of the plug assembly, whether to encode a signal of the signals using a first communication protocol or a second communication protocol based on a data transmission speed.

15. A transceiver device comprising:
a memory to store computer-executable instructions; and
a processor, coupled to the memory, that facilitates execution of the computer-executable instructions to perform operations, comprising:
receiving a set of signals from a first device;
encoding the set of signals to generate a set of encoded signals; and
transmitting the set of encoded signals via four or less twin axial cables, comprising a first twin axial cable and a second twin axial cable, the first twin axial cable being configured for transmitting a first encoded signal of the set of encoded signals in a first direction at a first transmission rate and the second twin axial cable being configured for transmitting a second encoded signal of the set of encoded signals in the first direction at a second transmission rate simultaneously with the transmitting of the first encoded signal, and the second transmission rate being different from the first transmission rate, wherein a second processor is integrated with a head of the first twin axial cable and connected to an interconnect to facilitate connecting the first twin axial cable to the interconnect, the i

Assignees

• Applied Micro Circuits Corp
• Macom Connectivity Solutions Llc

Inventors

• Dabiri Dariush
• Gupta Tarun
• Nagapudi Venkatesh

Classifications

• H03M13/253

  with concatenated codes · CPC title

• H04L5/14

  Two-way operation using the same type of signal, i.e. duplex · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• H04L1/0041 Primary

  Arrangements at the transmitter end · CPC title