Density function centric signal processing

Patent metadata

Field	Value
Publication number	US-9787341-B2
Application number	US-201314085898-A
Country	US
Kind code	B2
Filing date	Nov 21, 2013
Priority date	Nov 21, 2012
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

First claim

Having thus described various embodiments of the invention, what is claimed as new and desired to be protected by Letters Patent includes the following:

1. An apparatus for direct current (DC) offset estimation, the apparatus comprising:
a quantile value circuit comprising a plurality of quantile filters configured to determine a plurality of quantile values of an input signal; and
a signal processor configured to calculate a weighted average of the plurality of quantile values to yield a DC offset estimate,
wherein each quantile filter comprises:
a comparator configured to receive the input signal the input signal, the quantile value, and a first control signal, compare the input signal and the quantile value, and provide a difference signal,
a level shifter configured to receive the difference signal and a second control signal, adjust a level of the difference signal, and provide a shifted signal,
a monotonic transfer function component configured to receive the shifted signal, determine a magnitude of the shifted signal, and provide a transfer function signal, and
a latched integrator configured to receive the transfer function signal, suppress transient characteristics of the transfer function signal, and provide the quantile value.

2. The circuit of claim 1 , wherein the comparator is further configured to receive a parameter from the first control signal that determines a time period over which the comparator filters the communications signal.

3. The circuit of claim 1 , wherein the comparator is further configured to receive a parameter from the first control signal that determines a response time during which the comparator functions.

4. An apparatus for fine direct current (DC) offset estimation, the apparatus comprising:
a DC offset estimation circuit configured to provide a DC offset estimate of an input signal;
an adaptive prescaler configured to scale the DC offset estimate and provide a scaled signal; and
a selector circuit configured to receive the input signal and the scaled signal and provide the scaled signal to the DC offset estimation circuit,
wherein the DC offset estimation circuit is further configured to perform a fine DC offset estimation of the scaled signal provided by the selector circuit.

5. The circuit of claim 4 , wherein the DC offset estimation circuit comprises:
a quantile value circuit configured to determine a plurality of quantile values of the input signal, and
a signal processor configured to calculate a weighted average of the quantile values to yield the DC offset estimate.

6. The circuit of claim 5 , wherein the quantile value circuit comprises a plurality of quantile filters, each quantile filter configured to produce a quantile value and comprising:
a comparator configured to receive the input signal, the quantile value, and a first control signal, compare the input signal and the quantile value, and provide a difference signal,
a level shifter configured to receive the difference signal and a second control signal, adjust a level of the difference signal, and provide a shifted signal,
a monotonic transfer function component configured to receive the shifted signal, determine a magnitude of the shifted signal, and provide a transfer function signal, and
a latched integrator configured to receive the transfer function signal, suppress transient characteristics of the transfer function signal, and provide the quantile value.

Assignees

• Alarm Com Inc

Inventors

• Briancon Alain Charles
• Epard Marc Anthony
• Lutes Robert Leon
• Lancaster John Berns
• Johnson Jerald Frederic
• Kabler Ronald Byron

Classifications

• H04B2001/305

  using DC offset compensation techniques · CPC title

• H04B1/30 Primary

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title