Switching control systems

Patent metadata

Field	Value
Publication number	US-9787299-B2
Application number	US-201214367270-A
Country	US
Kind code	B2
Filing date	Dec 6, 2012
Priority date	Dec 23, 2011
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

We describe a system for controlling very large numbers of power semiconductor switching devices ( 132 ) to switch in synchronization. The devices are high power devices, for example carrying hundreds of amps and/or voltages of the order of kilovolts. In outline the system comprises a coordinating control system ( 110, 120 ), which communicates with a plurality of switching device controllers ( 130 ) to control the devices into a plurality of states including a fully-off state, a saturated-on state, and at least one intermediate state between the fully-off and saturated-on states, synchronizing the devices in the at least one intermediate state during switching.

First claim

The invention claimed is:

1. A power semiconductor switching device control system for controlling a plurality of power semiconductor switching devices to switch in synchronisation, the system comprising:
a coordinating control system; and
a plurality of switching device controllers each coupled to said coordinating control system;
wherein each said switching device controller is configured to control one or more respective said power semiconductor switching devices into a plurality of states including a fully-off state, a saturated-on state, and at least one intermediate state between said fully-off state and said saturated-on state;
wherein said coordinating control system is configured to control said switching devices to switch in synchronism by controlling said switching device controllers; and
wherein said coordinating control system is further configured to:
control said switching device controllers to control said power semiconductor switching devices from an initial state comprising one of said fully-off state and said saturated-on state into said intermediate state;
maintain said power semiconductor switching devices in said intermediate state to synchronize switching of said devices; and then
control said switching device controllers to control said power semiconductor switching devices from said intermediate state into a final state comprising the other of said fully-off state and said saturated-on state.

2. A control system as claimed in claim 1 wherein each said switching device controller is configured to control said one or more respective said power semiconductor switching devices into a plurality of said intermediate states between said fully-off state and said saturated-on state; and wherein said coordinating control system is further configured to control said switching device controllers to control said power semiconductor switching device into each of said intermediate states when switching between said fully-off state and said saturated-on state, and to maintain said power semiconductor switching devices in each of said intermediate statues before transitioning to the next said intermediate state, to synchronize switching of said devices.

3. A control system as claimed in claim 1 wherein a or the said intermediate state comprises a ready-on state, wherein in said ready-on state a said power semiconductor switching device has a current intermediate between a fully-off current for a saturated-on current.

4. A control system as claimed in claim 1 , wherein a or the said intermediate state comprises an active low voltage state, wherein in said active low voltage state a said power semiconductor switching device supports a voltage intermediate between a fully-off voltage and a saturated-on voltage.

5. A control system as claimed in claim 1 , wherein said coordinating control system and each of said switching device controllers comprise a respective data communications interface for data communications between said coordinating control system and said switching device controllers; and
wherein said coordinating control system is further configured to control said switching device controllers to control said power semiconductor switching devices by:
issuing a control signal to said switching device controllers to control said power semiconductor switching devices from said initial state to said intermediate state;
receiving a confirmation signal from said switching device controllers that said intermediate state has been achieved;
waiting until each of said switching device controllers has confirmed that said intermediate state has been achieved; and then
issuing a control signal to said switching device controllers to control said power semiconductor switching devices from said intermediate state to a subsequent said state.

6. A control system as claimed in claim 5 wherein said data communication interfaces comprise packet data communication interfaces.

7. A control system as claimed in claim 6 wherein said control signal and said confirmation signal comprises real time packet data communication signals.

8. A control system as claimed in claim 1 further comprising said power semiconductor switching devices, wherein said power semiconductor switching devices are connected to define a set of strings of series-connected devices, and wherein corresponding devices in each string of said set are connected in parallel.

9. A control system as claimed in claim 1 wherein said power semiconductor switching devices comprise IGBTs.

10. A coordinating control system for controlling a plurality of switching device controllers each coupled to the coordinating control system for switching a plurality of power semiconductor switching devices in synchronism, wherein each said switching device controller is configured to control one or more respective said power semiconductor switching devices into a plurality of states including a fully-off state, a saturated-on state, and at least one intermediate state between said fully-off state and said saturated-on state, the coordinating control system comprising:
a system to control said power semiconductor switching devices to switch in synchronism by controlling said switching device controllers;
wherein said system to control said power semiconductor switching devices is configured to:
control said switching device controllers to control said power semiconductor switching devices from an initial state comprising one of said fully-off state and said saturated-on state into said intermediate state;
maintain said power semiconductor switching devices in said intermediate state to synchronize switching of said devices; and then
control said switching device controllers to control said power semiconductor switching devices from said intermediate state into a final state comprising the other of said fully-off state and said saturated-on state.

Assignees

• Amantys Ltd
• Reinhausen Maschf Scheubeck

Inventors

• Snook Mark
• Shelton Edward
• Parker Stephen
• Vit Matteo

Classifications

• H03K17/163

  Soft switching · CPC title

• H03K17/127

  in composite switches · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H03K17/16 Primary

  Modifications for eliminating interference voltages or currents · CPC title

• H03K17/107

  in composite switches · CPC title