Operation of double-base bipolar transistors with additional timing phases at switching transitions

Patent metadata

Field	Value
Publication number	US-9787298-B2
Application number	US-201615267085-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Nov 18, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

First claim

What is claimed is:

1. A method for operating a bidirectional bipolar power transistor which has two distinct n-type emitter/collector regions on opposite faces of a p-type semiconductor die, and two distinct p-type base contact regions on the opposite faces of the die, comprising:
1) in a transistor-ON timing phase, when minimal voltage drop is desired, biasing a first one of the base contact regions, which is closest to whichever of the emitter/collector regions is more positive at the moment, to a voltage which causes bipolar conduction, to thereby reduce the voltage drop between the two emitter/collector regions; and thereafter
2) in a first pre-turnoff timing phase, shorting each of the base contact regions to the respectively nearest one of the emitter/collector regions, to thereby increase the voltage drop between the two emitter/collector regions; and thereafter
3) in a second pre-turnoff timing phase, biasing the second base contact regions negative with respect to its nearest emitter/collector region, to thereby reduce the minority carrier concentration in the bulk base region.

2. The method of claim 1 , wherein step 3) has a shorter duration than does step 2).

3. The method of claim 1 , wherein the semiconductor die is silicon.

4. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 1 .

5. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 1 , and which includes a Schottky barrier diode which is connected to block turn-on of reverse conduction during periods of negative base drive.

6. A method for operating a bidirectional bipolar power transistor which has two distinct n-type emitter/collector regions on opposite faces of a p-type semiconductor die, and two distinct p-type base contact regions on the opposite faces of the die, comprising, when a first one of the emitter/collector regions is more positive than a second one of the emitter/collector regions:
0) in a diode-ON timing phase, shorting a first one of the base contact regions to the first emitter/collector region, which is the nearest thereto, to thereby initiate conduction between the two emitter/collector regions; and thereafter
1) in a transistor-ON timing phase, when minimal voltage drop is desired, biasing the first base contact region to a voltage which causes bipolar conduction, to thereby reduce the voltage drop between the two emitter/collector regions; and thereafter
2) in a first pre-turnoff timing phase, shorting each of the base contact regions to the respectively nearest one of the emitter/collector regions, to thereby increase the voltage drop between the two emitter/collector regions; and thereafter
3) in a second pre-turnoff timing phase, biasing the second base contact regions negative with respect to the second emitter/collector region; and thereafter
4) shorting the second base contact region to the second emitter/collector region, to keep the device turned off.

7. The method of claim 6 , wherein step 3) has a shorter duration than step 2).

8. The method of claim 6 , wherein the semiconductor die is silicon.

9. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 6 .

10. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 6 , and which includes a Schottky barrier diode which is connected to block turn-on of reverse conduction during periods of negative base drive.

11. A method for operating a bidirectional bipolar transistor which has two first-conductivity-type emitter/collector regions in distinct locations separated by a bulk second-conductivity-type base region, and two distinct second-conductivity-type base contact regions which connect to the bulk base region in mutually separate locations, comprising:
1) in a transistor-ON timing phase, when minimal voltage drop is desired, biasing a first one of the base contact regions, which is closer than a second one of the base contact regions to whichever of the emitter/collector regions is positioned to act as the collector, as defined by externally applied voltage polarity, to a voltage which causes bipolar conduction to reduce the voltage drop between the two emitter/collector regions; and thereafter
2) in a first pre-turnoff timing phase, shorting each of the base contact regions to the respectively nearest one of the emitter/collector regions; and thereafter
3) in a second pre-turnoff timing phase, biasing the second base contact regions with a polarity opposite to that applied to the first base contact region in step 1), to thereby reduce the minority carrier concentration in the bulk base region; and thereafter
4) turning the device off.

12. The method of claim 11 , wherein the first conductivity type is n-type.

13. The method of claim 11 , wherein step 3) has a shorter duration than step 2).

14. The method of claim 11 , wherein the semiconductor die is silicon.

15. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 11 .

16. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 11 , and which includes a Schottky barrier diode which is connected to block turn-on of reverse conduction during periods of negative base drive.

17. A method for operating a bidirectional bipolar power transistor which has two distinct n-type emitter/collector regions on opposite faces of a p-type semiconductor die, and two distinct p-type base contact regions on the opposite faces of the die, comprising:
1) in a transistor-ON timing phase, when minimal voltage drop is desired, biasing a first one of the base contact regions, which is closest to whichever of the emitter/collector regions is more positive at the moment, to a voltage which causes bipolar conduction, to thereby reduce the voltage drop between the two emitter/collector regions; and thereafter
2) in a first pre-turnoff timing phase, shorting each of the base contact regions to the respectively nearest one of the emitter/collector regions, to thereby increase the voltage drop between the two emitter/collector regions; and thereafter
3) in a second pre-turnoff timing phase, biasing a second one of the base contact regions negative with respect to its nearest emitter/collector region, to thereby reduce the minority carrier concentration in the bulk base region; and
during step 3), using a diode to block current which would tend to turn on conduction in a direction opposite to that of step 1).

18. The method of claim 17 , wherein step 3) has a shorter duration than step 2).

19. The method of claim 17 , wherein the semiconductor die is silicon.

20. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 17 .

21. A gate driving circuit which is connected to a double-base bidirectional bipolar power transistor, and which is configured to implement the methods of claim 17 , and which includes a Schottky barrier diode which is connected to block turn-on of reverse conduction during periods of negative bas

Assignees

• Ideal Power Inc
• Ideal Power Inc

Inventors

• Alexander William C
• Blanchard Richard A

Classifications

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H01L29/16

  Electricity · mapped topic

• H01L29/0808

  Electricity · mapped topic

• H01L29/747

  Electricity · mapped topic

• H01L29/1008

  Electricity · mapped topic