System and method for a switched capacitor circuit

Patent metadata

Field	Value
Publication number	US-9787291-B1
Application number	US-201615385527-A
Country	US
Kind code	B1
Filing date	Dec 20, 2016
Priority date	Dec 20, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

In accordance with an embodiment, a method of operating a switched capacitor circuit includes pre-charging a capacitor using a voltage buffer having an input coupled to an input node of the switched capacitor circuit and an output coupled to the capacitor, coupling the input node to the capacitor, wherein a first charge is collected on the capacitor, and integrating the first charge using an integrator.

First claim

What is claimed is:

1. A method of operating a switched capacitor circuit, the method comprising:
pre-charging a capacitor using a voltage buffer having an input coupled to an input node of the switched capacitor circuit and an output coupled to the capacitor via a first switch;
coupling the input node to the capacitor via a second switch, wherein a first charge is collected on the capacitor; and
integrating the first charge using an integrator.

2. The method of claim 1 , further comprising:
quantizing the integrated first charge to form a quantized value; and
feeding back the quantized value to the capacitor.

3. The method of claim 2 , further comprising decimating the quantized value.

4. The method of claim 1 , wherein:
coupling the input node to the capacitor comprises coupling the input node to the capacitor via a resistor; and
the voltage buffer has a settling time of less than five times an RC time constant of the resistor and the capacitor.

5. A switched capacitor circuit comprising:
a capacitor;
a first switch having a first node coupled to an input port of the switched capacitor circuit and a second node coupled to the capacitor;
a voltage buffer having an input coupled to the first node of the first switch and an output coupled to the capacitor;
a second switch coupled between the output of the voltage buffer and the capacitor; and
a controller configured to
in a first phase, deactivate the first switch and activate the second switch, wherein the capacitor is disconnected from the input port via the first switch and the capacitor is connected to the output of the voltage buffer by the second switch, and
in a second phase after the first phase, activate the first switch and deactivate the second switch, wherein the capacitor is connected to the input port via the first switch and the capacitor is disconnected from the output of the voltage buffer by the second switch.

6. The switched capacitor circuit of claim 5 , further comprising an integrator coupled to the capacitor, the integrator configured to integrate charge of the capacitor.

7. The switched capacitor circuit of claim 5 , further comprising a resistor coupled between the input port of the switched capacitor circuit and the first node of the first switch.

8. The switched capacitor circuit of claim 7 , wherein the voltage buffer has a settling line of less than five time constants, wherein each time constant is a product of a resistance of the resistor and a capacitance of the capacitor.

9. The switched capacitor circuit of claim 5 , wherein the capacitor, voltage buffer, first switch and second switch are disposed on an integrated circuit.

10. An integrated circuit comprising:
a first capacitor network;
a first switch network coupled between an input pin of the integrated circuit and a first port of the first capacitor network;
a voltage buffer having an input coupled to the first port of the first capacitor network;
a second switch network coupled between an output of the voltage buffer and the first port of the first capacitor network; and
a controller configured to
in a first phase, deactivate the first switch network and activate the second switch network, wherein the first capacitor network is disconnected from the input pin via the first switch network and the first capacitor network is connected to the output of the voltage buffer by the second switch network, and
in a second phase after the first phase, activate the first switch network and deactivate the second switch network, wherein the first capacitor network is connected to the input pin via the first switch network and the first capacitor network is disconnected from the output of the voltage buffer by the second switch network.

11. The integrated circuit of claim 10 , further comprising:
an integration circuit coupled to a second port of the first capacitor network; and
a third switch network coupled between the integration circuit and the second port of the first capacitor network, wherein the controller is further configured to,
deactivate the third switch network during the first phase and the second phase, wherein the integration circuit is disconnected from the first capacitor network, and
activate the third switch network during a third phase after the second phase, wherein the integration circuit is connected to the first capacitor network.

12. The integrated circuit of claim 11 , wherein the controller is further configured to:
in the third phase, activate the second switch network and deactivate the first switch network; and
in a fourth phase after the third phase, activate the first switch network, deactivate the second switch network and activate the third switch network.

13. The integrated circuit of claim 12 , wherein:
the first capacitor network comprises a first capacitor and a second capacitor;
the voltage buffer comprises a first buffer having an input coupled to a first terminal of the first port and second buffer having an input coupled to a second terminal of the first port;
during the first phase and the third phase, the second switch network is configured to connect an output of the first buffer to a first terminal of the first capacitor, and to connect an output of the second buffer to a first terminal of the second capacitor; and
during the second phase and the fourth phase, the first switch network is configured to connect the first terminal of the first port to the first terminal of the first capacitor, and to connect the second terminal of the second port to the first terminal of the second capacitor.

14. The integrated circuit of claim 13 , wherein:
during the third phase and the fourth phase, the third switch network is configured to connect a second terminal of the first capacitor to a first input node of the integration circuit, and is configured to connect a second terminal of the second capacitor a second input node of the integration circuit; and
during the first phase and the second phase, the third switch network is configured to disconnect the second terminal of the first capacitor from the first input node of the integration circuit, disconnect the second terminal of the second capacitor from the second input node of the integration circuit, and connect the second terminal of the first capacitor to the second terminal of the second capacitor.

15. The integrated circuit of claim 14 , wherein the third switch network is further configured to connect the second terminal of the first capacitor and the second terminal of the second capacitor to a common mode reference voltage.

16. The integrated circuit of claim 11 , wherein the integration circuit comprises:
an amplifier having an input coupled to the first capacitor network; and
a capacitor coupled between the input of the amplifier and an output of an amplifier.

17. The integrated circuit of claim 10 , further comprising:
a quantizer having an input coupled to an output of the integration circuit; and
a digital to analog converter having an input coupled an output of the quantizer and an output coupled to the controller.

18. The integrated circuit of claim 10 , further comprising:
a resistor having a first end coupled to the input pin and a second end coupled to first switch network and the input of the voltage buffer.

19. The integrated circuit of claim 18 , wherein the voltage buffer has a settling time of less than five times an RC time constant of the resistor and a capacitance of the first capacitor network.

Assignees

• Infineon Technologies Ag

Inventors

• Reindl Christian
• Kropfitsch Michael
• Bogner Peter

Classifications

• H03M3/422

  having one quantiser only · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03H19/004 Primary

  Switched capacitor networks · CPC title

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title