Mismatch correction in differential amplifiers using analog floating gate transistors

Patent metadata

Field	Value
Publication number	US-9787263-B2
Application number	US-201615173217-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Nov 23, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An analog differential amplifier circuit, such as an operational transconductance amplifier (OTA), with input offset correction capability. First and second analog floating gate (AFG) devices each include a trim transistor connected in parallel with a series transistor in first and second input legs, respectively, of the amplifier. Floating gate electrodes in the AFG devices are differentially programmed to correct for error in the output signal in response to zero input differential voltage at its inputs. Temperature stability is attained by programming the floating gate electrodes to gate voltages above the floating gate transistors. In one embodiment, the AFG devices each include a second trim transistor sharing the same floating gate electrode; the sum of the currents conducted by the second trim transistors is added, by way of a current mirror, to the tail current applied to the first and second input legs.

First claim

What is claimed is:

1. An analog differential circuit, comprising:
a current source, for conducting a tail current from a first reference voltage;
a first input leg coupled between the current source and a second reference voltage, comprising:
a first input transistor, having a source/drain path and a gate, the gate receiving a first input voltage; and
a first load device connected in series with the source/drain path of the first input transistor;

a second input leg coupled between the current source and a second reference voltage, comprising:
a second input transistor, having a source/drain path and a gate, the gate receiving a second input voltage; and
a second load device connected in series with the source/drain path of the second input transistor;

an output circuit, coupled to the first and second input legs, and having an output node for presenting an output signal responsive to a difference between the first and second input voltages;
a first programmable resistive element connected in parallel with the first load device and comprising a first analog floating gate device including a first trim transistor having a source/drain path connected in parallel with the first load device and having a programmable floating gate programmed to a first gate voltage; and
a second programmable resistive element connected in parallel with the second load device and comprising a second analog floating gate device including a second trim transistor having a source/drain path connected in parallel with the second load device and having a programmable floating gate programmed to a second gate voltage;
wherein at least one of the gate voltages of the first and second analog floating gate devices is above the threshold voltage of its trim transistor.

2. The circuit of claim 1 , wherein each of the gate voltages of the first and second analog floating gate devices is above the threshold voltage of its trim transistor.

3. The circuit of claim 2 , wherein the first and second analog floating gate devices each further comprise:
a tunnel capacitor, having a first plate coupled to a programming node, and a second plate comprising at least a part of the floating gate electrode; and
a control capacitor, having a first plate coupled to the second reference voltage, and a second plate comprising at least a part of the floating gate electrode.

4. The circuit of claim 2 , wherein the first load device comprises a first series transistor, having a source/drain path connected in series with the source/drain path of the first input transistor, and having a gate connected to its drain;
wherein the second load device comprises a second series transistor, having a source/drain path connected in series with the source/drain path of the second input transistor, and having a gate connected to its drain;
and wherein the output circuit comprises:
a mirror leg, coupled between the first and second reference voltages, and coupled to the gate of the first series transistor to conduct a current mirrored with a current conducted by the first input leg responsive to the first input voltage; and
an output mirror leg having an output node for presenting an output current corresponding to a difference of a current mirrored with the first mirror leg and a current mirrored with a current conducted by the second input leg responsive to the second input voltage.

5. The circuit of claim 4 , wherein the first analog floating gate device further comprises a third trim transistor, having a source/drain path;
wherein the second analog floating gate device further comprises a fourth trim transistor, having a source/drain path;
wherein the floating gate electrode of the first analog floating gate device also serves as a gate of the third trim transistor;
wherein the floating gate electrode of the second analog floating gate device also serves as a gate of the fourth trim transistor;
and further comprising:
a tail current mirror comprising:
a first tail transistor having a source/drain path coupled between the first and second reference voltages to conduct a current corresponding to currents conducted by the third and fourth trim transistors; and
a second tail transistor having a source/drain path connected between the first reference voltage and the first and second input legs, and a gate coupled to the first tail transistor so that the second tail transistor conducts a current corresponding to the current conducted by the first tail transistor.

6. The circuit of claim 5 , wherein the source/drain paths of the third and fourth trim transistors are connected in parallel;
wherein the first tail transistor has a gate connected to its drain;
wherein the gate of the second tail transistor is connected to the gate and drain of the first tail transistor;
and wherein the source/drain path of the first tail transistor is connected in series with the parallel-connected source/drain paths of the third and fourth trim transistors.

7. The circuit of claim 5 , wherein the first analog floating gate device is programmed to a first gate voltage above the threshold voltage of the first and third trim transistors;
and wherein the second analog floating gate device is programmed to a second gate voltage above the threshold voltage of the second and fourth trim transistors.

8. The circuit of claim 5 , wherein the first and second input transistors are p-channel metal-oxide semiconductor (MOS) transistors;
wherein the first and second series transistors, and the first and second trim transistors, are n-channel MOS transistors;
and wherein the first reference voltage is a positive power supply voltage and the second reference voltage is a ground voltage.

9. The circuit of claim 5 , wherein the first and second input transistors are n-channel MOS transistors;
wherein the first and second series transistors, and the first and second trim transistors, are p-channel MOS transistors;
and wherein the first reference voltage is a ground voltage and the second reference voltage is a positive power supply voltage.

10. The circuit of claim 1 , further comprising:
programming circuitry, coupled to the first and second analog floating gate devices, for programming the first and second gate voltages at a differential corresponding to an input offset of the circuit.

11. A differential amplifier circuit comprising:
a tail current source, for conducting a tail current from a first reference voltage;
a first input leg coupled between the current source and a second reference voltage, comprising:
a first input transistor, having a source/drain path and a gate, the gate receiving a first input voltage; and
a first load device connected in series with the source/drain path of the first input transistor;

a second input leg coupled in parallel with the first input leg between the current source and a second reference voltage, comprising:
a second input transistor, having a source/drain path and a gate, the gate receiving a second input voltage; and
a second load device connected in series with the source/drain path of the second input transistor;

an output circuit, coupled to the first and second input legs, for presenting an output corresponding to a difference between the first and second input voltages;
a first analog floating gate device, comprising:
a floating gate electrode;
a tunnel capacitor, having a plate coupled to a programming node and capacitively coupled to the floating gate electrode;
a first trim transistor, having a source/drain path connected in parallel with the first load device, the floating gate electrode serving as a gate of the first trim transistor; and
a second trim transistor, having a source/drai

Assignees

• Texas Instruments Inc

Inventors

• Patel Ujas Natvarlal
• Marshall Andrew
• Stiegler Harvey J
• Jarreau Keith M

Classifications

• H03F1/0205 Primary

  in transistor amplifiers · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2203/45121

  A floating gate element being part of a dif amp · CPC title

• H03F3/45

  Differential amplifiers (differential sense amplifiers G11C7/062) · CPC title

• H03F3/45273 Primary

  Mirror types · CPC title