Driver and driving control method for power converter

Patent metadata

Field	Value
Publication number	US-9787183-B2
Application number	US-201414259168-A
Country	US
Kind code	B2
Filing date	Apr 23, 2014
Priority date	Jul 19, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first PMOS transistor. The level shift circuit provides an output signal, wherein the output signal has a first operation voltage and a second operation voltage. When the output signal received by the negative voltage generator is the first operation voltage, the negative voltage generator outputs the first operation voltage. When the output signal received by the negative voltage generator is the second operation voltage, the negative voltage generator generates and outputs a third operation voltage, and the third operation voltage is lower than the second operation voltage. A control terminal of the first PMOS transistor is coupled to an output terminal of the negative voltage generator. An output terminal of the first PMOS transistor provides a driving voltage.

First claim

What is claimed is:

1. A driver for a power converter, comprising:
a level shift circuit, providing an output signal, wherein the output signal has a first operation voltage and a second operation voltage;
a negative voltage generator, coupled to the level shift circuit, wherein the negative voltage generator outputs the first operation voltage when the output signal received by the negative voltage generator is the first operation voltage, and the negative voltage generator generates and outputs a third operation voltage when the output signal received by the negative voltage generator is the second operation voltage, the third operation voltage being lower than the second operation voltage; and
a first PMOS transistor, having a control terminal and an output terminal, wherein the control terminal of the first PMOS transistor is coupled to an output terminal of the negative voltage generator, and the output terminal of the first PMOS transistor provides a driving voltage.

2. The driver as claimed in claim 1 , wherein the first operation voltage is larger than the second operation voltage.

3. The driver as claimed in claim 2 , wherein the third operation voltage is between the second operation voltage and zero voltage.

4. The driver as claimed in claim 1 , wherein the driving voltage is identical with the first operation voltage.

5. The driver as claimed in claim 1 , wherein the driver further comprises:
a high side driving unit, coupled to the output terminal of the first PMOS transistor to receive the driving voltage for use in driving a high side switch.

6. The driver as claimed in claim 1 , wherein the negative voltage generator further comprises:
a capacitor having a first terminal coupled to an output terminal of the level shift circuit;
a diode, having a first terminal coupled to a second terminal of the capacitor and a second terminal receiving the second operation voltage; and
an inverter, having an input terminal coupled to the second terminal of the diode, an output terminal serving as an output terminal of the negative voltage generator, a first power input terminal coupled to the output terminal of the level shift circuit and a first terminal of the capacitor, and a second power input terminal coupled to the first terminal of the diode.

7. The driver as claimed in claim 6 , wherein the third operation voltage is generated in a common node when the negative voltage generator receives the second operation voltage from the level shift circuit, the common node being a coupling point of the diode and the capacitor.

8. The driver as claimed in claim 6 , wherein a first NMOS transistor is configured as the diode, a control terminal of the first NMOS transistor being coupled to a first terminal to serve as the first terminal of the diode, and a second terminal of the first NMOS transistor serving as the second terminal of the diode.

9. The driver as claimed in claim 6 , wherein a second PMOS transistor and a second NMOS transistor is configured as the inverter, a control terminal of the second PMOS transistor being coupled to a control terminal of the second NMOS transistor to serve as the input terminal of the inverter, a second terminal of the second PMOS transistor serving as the first power input terminal of the inverter, a second terminal of the second NMOS transistor serving as the second power input terminal of the inverter, and a first terminal of the second PMOS transistor being coupled to a first terminal of the second NMOS transistor to serve as the output terminal of the inverter.

10. The driver as claimed in claim 6 , wherein when the negative voltage generator receives the second operation voltage from the level shift circuit, a relationship between a cross-voltage from an input terminal to the control terminal of the first PMOS transistor and the second operation voltage is shown in the equation below:
VSG= 2×( VCC−VSW )− Vf , and VSG>VCC−VSW,

wherein VSG is the cross-voltage, VCC is a fourth operation voltage received by the input terminal of the first PMOS transistor, VSW is the second operation voltage, and Vf is a forward bias of the diode.

11. A driving control method for a power converter, comprising:
providing a level shift circuit, the level shift circuit providing an output signal, wherein the output signal has a first operation voltage and a second operation voltage;
providing a negative voltage generator, wherein the negative voltage generator outputs the first operation voltage when the output signal received by the negative voltage generator is the first operation voltage, and the negative voltage generator generates and outputs a third operation voltage when the output signal received by the negative voltage generator is the second operation voltage, the third operation voltage being lower than the second operation voltage; and
providing a first PMOS transistor, wherein a control terminal of the first PMOS transistor is coupled to an output terminal of the negative voltage generator, and an output terminal of the first PMOS transistor provides a driving voltage.

12. The driving control method as claimed in claim 11 , wherein the first operation voltage is larger than the second operation voltage.

13. The driving control method as claimed in claim 12 , wherein the third operation voltage is between the second operation voltage and zero voltage.

14. The driving control method as claimed in claim 11 , wherein the driving voltage is identical with the first operation voltage.

15. The power control method as claimed in claim 11 , further comprising:
providing the driving voltage to a high side driving unit, the high side driving unit receiving the driving voltage for use in driving a high side switch.

16. The driving control method as claimed in claim 11 , wherein the negative voltage generator comprises:
a capacitor having a first terminal coupled to an output terminal of the level shift circuit;
a diode, having a first terminal coupled to a second terminal of the capacitor and a second terminal receiving the second operation voltage; and
an inverter, having an input terminal coupled to the second terminal of the diode, an output terminal serving as an output terminal of the negative voltage generator, a first power input terminal coupled to the output terminal of the level shift circuit and the first terminal of the capacitor, and a second power input terminal coupled to the first terminal of the diode.

17. The driving control method as claimed in claim 16 , wherein the third operation voltage is generated in a common node when the negative voltage generator receives the second operation voltage from the level shift circuit, the common node being a coupling point of the diode and the capacitor.

18. The driving control method as claimed in claim 16 , wherein when the negative voltage generator receives the second operation voltage from the level shift circuit, a relationship between a cross-voltage from an input terminal to the control terminal of the first PMOS transistor and the second operation voltage is shown in the equation below:
VSG= 2×( VCC−VSW )− Vf , and VSG>VCC−VSW,

wherein VSG is the cross-voltage, VCC is a fourth operation voltage received by the input terminal of the PMOS transistor, VSW is the second operation voltage, and Vf is a forward bias of the diode.

Assignees

• Upi Semiconductor Corp

Inventors

• Chen wei-ling

Classifications

• H02M2001/0006

  Electricity · mapped topic

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K2217/0081

  Power supply means, e.g. to the switch driver · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title