Laser diode chip and flip chip type laser diode package structure

Patent metadata

Field	Value
Publication number	US-9787053-B2
Application number	US-201615197790-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Jun 20, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A laser diode chip includes a removable substrate, a first semiconductor layer disposed on the removable substrate, an emitting layer disposed on one part of the first semiconductor layer, a second semiconductor layer disposed on the emitting layer and forming a ridge mesa, a current conducting layer disposed on another part of the first semiconductor layer, a patterned insulating layer covering the second semiconductor layer and the current conducting layer and including a first zone and a second zone which respectively expose a part of the current conducting layer and a part of the second semiconductor layer, a first electrode and a second electrode respectively disposed on the first zone and the second zone. A projection of the ridge mesa projected to the removable substrate covers a part of projections of the first electrode and the second electrode projected to the removable substrate.

First claim

What is claimed is:

1. A laser diode chip, comprising:
a removable substrate;
a first semiconductor layer, disposed on the removable substrate.
an emitting layer, disposed on a part of the first semiconductor layer;
a second semiconductor layer, disposed on the emitting layer and fonning a ridge mesa;
at least one current conducting layer, disposed on a part of the first semiconductor layer, wherein the at least one current conducting layer is electrically connected with the first semiconductor layer and isolated from the second semiconductor layer;
a patterned insulating layer, covering the first semiconductor layer, the emitting layer, the second semiconductor layer, and the at least one current conducting layer and comprising a first zone and a second zone, wherein the first zone exposes a part of the at least one current conducting layer, and the second zone exposes a part of the second semiconductor layer;
a first electrode, disposed in the first zone of the patterned insulating layer; and
a second electrode, disposed in the second zone of the patterned insulating layer, wherein a projection of the ridge mesa projected to the first semiconductor layer respectively covers a part of a projection of the first electrode and a part of a projection of the second electrode projected to the first semiconductor layer, wherein polarity of the first electrode and polarity of the second electrode are reversed, and the first electrode and the second electrode are disposed at the same side of the first semiconductor layer, and wherein the first electrode and the second electrode are approximately coplanar.

2. The laser diode chip as claimed in claim 1 , wherein the number of the at least one current conducting layer is one, and the current conducting layer is located at one side of the ridge mesa.

3. The laser diode chip as claimed in claim 1 , wherein the number of the at least one current conducting layer is two, and the two current conducting layers are located at two sides of the ridge mesa.

4. The laser diode chip as claimed in claim 1 , wherein a cross-section of the laser diode chip crosscuts the ridge mesa and the at least one current conducting layer, and a width of the cross-section of the laser diode chip is less than 100 micrometers.

5. The laser diode chip as claimed in claim 1 , wherein a cross-section of the laser diode chip crosscuts the ridge mesa and the at least one current conducting layer, a ratio between a width of the ridge mesa and a width of the cross-section of the laser diode chip is approximately from 0.01 to 0.5, and a range of the width of the ridge mesa is approximately from 1 to 50 micrometers.

6. The laser diode chip as claimed in claim 1 , wherein the first electrode and the second electrode are electrically connected with a third electrode and a fourth electrode of a package substrate.

7. The laser diode chip as claimed in claim 1 , wherein a width of an open of the second zone of the patterned insulating layer is approximately the same as a width of the ridge mesa of the second semiconductor layer.

8. The laser diode chip as claimed in claim 1 , wherein a width of at least one open of the first zone of the patterned insulating layer is approximately the same as a width of the at least one current conducting layer.

9. A flip chip type laser diode package structure, comprising:
a laser diode chip, comprising:
a first semiconductor layer;
an emitting layer, disposed on a part of the first semiconductor layer;
a second semiconductor layer, disposed on the emitting layer and forming a ridge mesa;
at least one current conducting layer, disposed on a part of the first semiconductor layer, wherein the at least one current conducting layer is electrically connected with the first semiconductor layer and isolated from the second semiconductor layer;
a patterned insulating layer, covering the first semiconductor layer, the emitting layer, the second semiconductor layer, and the at least one current conducting layer and comprising a first zone and a second zone, wherein the first zone exposes a part of the at least one current conducting layer, and the second zone exposes a part of the second semiconductor layer;
a first electrode, disposed in the first zone of the patterned insulating layer; and
a second electrode, disposed in the second zone of the patterned insulating layer, wherein a projection of the ridge mesa projected to the first semiconductor layer respectively covers a part of a projection of the first electrode and a part of a projection of the second electrode projected to the first semiconductor layer, wherein polarity of the first electrode and polarity of the second electrode are reversed, and the first electrode and the second electrode are disposed at the same side of the first semiconductor layer; and

a package substrate; wherein the laser diode chip is flipped on and electrically connected with the package substrate, the package substrate comprising:
a second substrate;
a third electrode, disposed on a part of the second substrate and contacting the first electrode; and
a fourth electrode, disposed on a part of the second substrate and kept a distance from the third electrode, wherein the fourth electrode contacts the second electrode.

10. The flip chip type laser diode package structure as claimed in claim 9 , wherein the number of the at least one current conducting layer is one, and the current conducting layer is located at one side of the ridge mesa.

11. The flip chip type laser diode package structure as claimed in claim 9 , wherein the number of the at least one current conducting layer is two, and the two current conducting layers are located at two sides of the ridge mesa.

12. The flip chip type laser diode package structure as claimed in claim 9 , wherein a cross-section of the laser diode chip crosscuts the ridge mesa and the at least one current conducting layer, and a width of the cross-section of the laser diode chip is less than 100 micrometers.

13. The flip chip type laser diode package structure as claimed in claim 9 , wherein a cross-section of the laser diode chip crosscuts the ridge mesa and the at least one current conducting layer, a ratio between a width of the ridge mesa and a width of the cross-section of the laser diode chip is approximately from 0.01 to 0.5, and a range of the width of the ridge mesa is approximately from 1 to 50 micrometers.

14. The flip chip type laser diode package structure as claimed in claim 9 , wherein the first electrode and the second electrode are approximately coplanar.

15. The flip chip type laser diode package structure as claimed in claim 9 , wherein a width of an open of the second zone of the patterned insulating layer is approximately the same with a width of the ridge mesa of the second semiconductor layer.

16. The flip chip type laser diode package structure as claimed in claim 9 , wherein a width of at least one open of the first zone of the patterned insulating layer is approximately the same with a width of the at least one current conducting layer.

Assignees

• Playnitride Inc

Inventors

• Wu Chih-Ling
• Lo Yu-Yun

Classifications

• H01S5/04257

  having positive and negative electrodes on the same side of the substrate · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H01S5/2205

  comprising special burying or current confinement layers · CPC title