Improving signaling performance in connector design

Patent metadata

Field	Value
Publication number	US-9787028-B2
Application number	US-201213997893-A
Country	US
Kind code	B2
Filing date	Mar 31, 2012
Priority date	Mar 31, 2012
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Apparatus and methods of arranging ground pins and signal pins in a card connector includes arranging a signal pins and ground pins in a card connector into at least six (6) columns divided between a primary side and a secondary side of the connector.

First claim

We claim:

1. A card connector comprising:
a primary side and a secondary side disposed on opposite sides of a single card receiving slot, wherein a number of columns of pins on each of the primary side and the secondary side is at least six, and wherein the pins include signal pins and ground pins that are equally disposed on both the primary side and the secondary side, and at least some of the signal pins are adjacently arranged into a plurality of groups, and wherein the number of columns of pins on both the primary side and the secondary side includes a first group of two columns of signal pins, a second group of two columns of ground pins, and a third group of two columns of signal pins.

2. The connector of claim 1 , wherein the two columns of ground pins are positioned in between at least one column of signal pins in the first group and one column of signal pins in the third group.

3. The connector of claim 1 , wherein the two columns of ground pins in the second group are adjacent to one another.

4. The connector of claim 1 , wherein at least two signal pins in the first group of two columns of signal pins or in the second group of two columns of signal pins are configured as a differential pair.

5. The connector of claim 1 , wherein a distance between two signal pins in the first group or in the third group is three pitches.

6. The connector of claim 1 , further comprising:
a fourth group of two columns of ground pins, wherein the two columns of signal pins in the first group, the two columns of ground pins in the second group, and the two columns of signal pins in the third group are positioned in between a first column of ground pins of the fourth group and a second column of ground pins of the fourth group.

7. The connector of claim 1 , wherein the signal pins in the first group or the signal pins in the third group are aligned at an angle with the ground pins in the second group.

8. The connector of claim 1 , wherein a column of ground pins in the second group is positioned in between two columns of signal pins from the columns of signal pins in the first group and in the third group.

9. The connector of claim 1 , wherein a ground pin in a first column of ground pins and a ground pin in a second column of ground pins are aligned horizontally.

10. The connector of claim 1 , wherein a number of columns of pins on the primary side is equal to a number of columns of pins of the secondary side.

11. A computer-implemented method comprising:
assigning signal pins and ground pins of a card connector into at least six columns, wherein the at least six columns are assigned to each of a primary side and a secondary side of the card connector, and wherein the primary side and the secondary side are disposed on opposite sides of a single receiving card slot, and the at least six columns of signal pins and ground pins include at least two columns of ground pins and at least some of the signal pins are adjacently arranged into a plurality of groups, and wherein the number of columns of pins on both the primary side and the secondary side includes a first group of two columns of signal pins, a second group of two columns of ground pins, and a third group of two columns of signal pins.

12. The method of claim 11 , wherein the two columns of ground pins are positioned adjacent to one another.

13. The method of claim 11 , wherein the two columns of ground pins are separated by at least one column of signal pins.

14. The method of claim 11 , wherein a ground pin in a first column of ground pins and a ground pin in a second column of ground pins are aligned horizontally.

15. The method of claim 11 , wherein the at least six columns of signal pins and ground pins include four columns of signal pins.

16. The method of claim 15 , wherein the at least six columns are divided equally between the primary side and the secondary side of the card connector.

17. A system comprising:
a processor; and
a system board coupled to the processor and configured to accommodate a plurality of components via connectors, wherein one or more of the connectors includes at least six columns of signal pins and ground pins that are equally disposed on each of a primary side and a secondary side of the connector, wherein the primary side and the secondary side are disposed on opposite sides of a single card receiving slot, and at least some of the signal pins are adjacently arranged in a plurality of groups, wherein the connector is configured to include two additional columns of ground pins with one positioned on a far end of the primary side and another positioned on a far end of the secondary side.

18. The system of claim 17 , wherein the connector is configured to include differential pairs in adjacent two columns of signal pins.

19. The system of claim 17 , wherein the at least six columns of signal pins and grounds pins include two columns of ground pins positioned adjacent to one another.

20. The system of claim 17 , wherein the at least six columns of signal pins and grounds pins include two columns of ground pins separated by at least one column of signal pins.

21. The system of claim 17 , wherein the at least six columns of signal pins and grounds pins include two columns of ground pins, and wherein a ground pin in a first column of ground pins and a ground pin in a second column of ground pins are aligned horizontally.

22. The system of claim 17 , wherein the at least six columns of signal pins and grounds pins include four columns of signal pins.

23. The system of any of the claim 17 , wherein the at least six columns of signal and ground pins are divided equally between the primary side and the secondary side of the connector.

Assignees

• Enriquez-Shibayama Raul
• Xiao Kai
• Li Xiang
• Intel Corp

Inventors

• Enriquez-Shibayama Raul
• Xiao Kai
• Li Xiang

Classifications

• H01R2201/06

  for computer periphery · CPC title

• H01R13/6471

  by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal] · CPC title

• H01R12/737 Primary

  Printed circuits being substantially perpendicular to each other (for printed connections H05K3/366) · CPC title

• H01R13/6461 Primary

  Means for preventing cross-talk · CPC title