Backside integration of RF filters for RF front end modules and design structure

Patent metadata

Field	Value
Publication number	US-9786835-B2
Application number	US-201514712092-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	Jan 20, 2012
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

First claim

What is claimed:

1. A semiconductor structure, comprising:
a device at a front side of a substrate;
a radio frequency (RF) filter at a backside of the substrate;
at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device;
a second substrate conductor extending from the front side of the substrate to the backside of the substrate; and
a bond pad on the backside of the substrate and in contact with the second substrate conductor,
wherein:
the substrate is composed of silicon;
the RF filter is encapsulated at the backside of the substrate;
the second substrate conductor is separate from the at least one substrate conductor; and
the bond pad is outside of the encapsulation of the RF filter, such that the bond pad provides an external electrical connection at the backside of the substrate.

2. The structure of claim 1 , further comprising:
a buried insulator layer on the front side of the substrate; and
a semiconductor layer on the buried oxide layer,
wherein the device is on the semiconductor layer.

3. The structure of claim 2 , wherein the device comprises a field effect transistor formed on the semiconductor layer.

4. The structure of claim 2 , wherein the at least one substrate conductor passes entirely through the substrate, the buried insulator layer, and the semiconductor layer.

5. The structure of claim 2 , wherein:
the buried insulator layer is composed of oxide; and
the semiconductor layer is composed of silicon.

6. The structure of claim 1 , further comprising an insulator layer on the front side of the substrate and around the device.

7. The structure of claim 6 , wherein the at least one substrate conductor extends entirely through the insulator layer.

8. The structure of claim 6 , wherein a top surface of the at least one substrate conductor is planar with a top surface of the insulator layer.

9. The structure of claim 6 , further comprising at least one interlevel dielectric (ILD) layer on the insulator layer.

10. The structure of claim 9 , further comprising a passivation layer on the at least one (ILD) layer.

11. The structure of claim 10 , further comprising:
a front side bond pad formed in an opening of the passivation layer; and
a solder material formed on the front side bond pad.

12. The structure of claim 1 , wherein the at least one substrate conductor comprises:
a core of electrically conductive material; and
a film of electrical insulator material around the core.

13. The structure of claim 12 , wherein the film of electrical insulator material directly contacts the substrate.

14. The structure of claim 1 , further comprising a backside insulator layer on the backside of the substrate.

15. The structure of claim 14 , wherein a lowermost surface of the backside insulator layer is planar with a lowermost surface of the at least one substrate conductor.

16. The structure of claim 14 , wherein the RF filter comprises:
a piezoelectric material bonded to the backside insulator layer;
a pair of conductive lines having interdigitated fingers on the piezoelectric material; and
an electrode extending continuously from the at least one substrate conductor to one of the pair of conductive lines.

17. The structure of claim 16 , further comprising a tapered sidewall spacer fotliied at a corner defined by the piezoelectric material and the backside insulator layer, wherein the electrode extends across the tapered sidewall spacer.

18. The structure of claim 1 , further comprising at least one sealing layer on the backside insulator layer and defining a cavity around the RF filter, wherein the RF filter is encapsulated at the backside of the substrate by the at least one sealing layer.

19. The structure of claim 18 , wherein an opening in the at least one sealing layer exposes the bond pad.

20. The structure of claim 18 , wherein the at least one sealing layer comprises:
a first sealing layer directly contacting the backside insulator layer, the first sealing layer comprising a vent hole; and
a second sealing layer directly contacting the first sealing layer, the second sealing layer filling the vent hole in the first sealing layer.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Adkisson James W
• Candra Panglijen
• Dunbar Thomas J
• Gambino Jeffrey P
• Jaffe Mark D
• Stamper Anthony K
• Wolf Randy L

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title