Organic light-emitting diode display and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9786729-B2
Application number	US-201514806415-A
Country	US
Kind code	B2
Filing date	Jul 22, 2015
Priority date	Feb 13, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An organic light-emitting diode (OLED) display and a method of manufacturing an OLED display are disclosed. In one aspect, the display includes a display substrate including a display area and a non-display area surrounding the display area. Also included is a thin film transistor (TFT) formed over the display area and including a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode. An OLED is formed over the display area and includes a first electrode electrically connected to the TFT, an intermediate layer, and a second electrode. A plurality of power wirings are formed over the non-display area and are electrically connected to the second electrode so as to form an electrode contact. The display also includes a plurality of insulating layers formed over the display substrate and configured to insulate the TFT, the OLED, and the power wirings from one another.

First claim

What is claimed is:

1. An organic light-emitting diode (OLED) display comprising:
a display substrate including a display area and a non-display area surrounding the display area;
a thin film transistor (TFT) formed over the display area, and comprising a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode;
an OLED formed over the display area and comprising a first electrode electrically connected to the TFT, an intermediate layer, and a second electrode;
a plurality of power wirings formed over the non-display area and electrically connected to the second electrode so as to form an electrode contact;
a plurality of insulating layers formed over the display substrate and configured to insulate the TFT, the OLED, and the power wirings from one another, wherein the insulating layers comprise first and second insulation layers, wherein the first insulating layer includes a plurality of contact holes and one opening, and wherein a portion of the power wirings is exposed via the opening; and
a wiring electrode formed over an outer surface of the first insulating layer and configured to electrically connect the second electrode to the power wirings, wherein the wiring electrode defines the contact holes.

2. The OLED display of claim 1 , wherein the wiring electrode is formed on the same layer as the first electrode and is electrically connected to the exposed portion of the power wirings, and wherein the second electrode is formed over the display area, and contacts at least a portion of the non-display area, and the wiring electrode.

3. The OLED display of claim 2 , wherein the first insulating layer includes an upper surface, a side surface, and a bottom surface formed between the first and second insulating layers, and wherein the wiring electrode is formed over the upper, side and bottom surfaces of the first insulating layer and the exposed portion of the power wirings.

4. The OLED display of claim 3 , wherein the wiring electrode is integrally formed.

5. The OLED display of claim 2 , wherein the contact holes expose a surface of a second one of the insulating layers formed below the first insulating layer.

6. The OLED display of claim 5 , wherein the depths of the contact holes are equal to or greater than about 2 micrometers.

7. The OLED display of claim 2 , wherein the power wirings, the wiring electrode, and the second electrode are electrically connected to one another so as to form an electrode contact portion.

8. The OLED display of claim 2 , wherein the display area includes a plurality of pixels, wherein the intermediate layer comprises an organic emission layer and at least one pattern layer stacked on at least one surface of the organic emission layer, wherein the organic emission layer is formed in each pixel, and wherein the at least one pattern layer is formed over the display area and the non-display area.

9. The OLED display of claim 8 , wherein the first insulating layer includes an upper surface and a bottom surface formed between the first insulating layer and a second one of the insulating layers, wherein the at least one pattern layer is formed over the wiring electrode and the upper and bottom surfaces of the first insulating layer, and
wherein the wiring electrode penetrates the at least one pattern layer and is electrically connected to the second electrode.

10. The OLED display of claim 8 , wherein the first insulating layer includes a side surface defining the contact holes, wherein the at least one pattern layer is not formed over the side surface of the first insulating layer, and
wherein the second electrode and the wiring electrode are directly connected to each other over the side surface of the first insulating layer.

11. The OLED display of claim 8 , wherein the at least one pattern layer comprises at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

12. The OLED display of claim 2 , wherein the power wirings comprise i) a first wiring formed on the same layer as the gate electrode and ii) a second wiring electrically connected to the first wiring and formed on the same layer as the source and drain electrodes.

13. The OLED display of claim 12 , wherein the insulating layers comprise a gate insulating layer, an interlayer insulating layer, a planarization layer, and a pixel-defining layer,
wherein the first wiring and the gate electrode are formed over the gate insulating layer,
wherein the second wiring, the source electrode, and the drain electrode are formed over the interlayer insulating layer, and
wherein the wiring electrode and the first electrode are formed over the planarization layer.

14. A method of manufacturing an organic light-emitting diode (OLED) display including a display substrate, the method comprising:
forming a thin film transistor (TFT) in a display area of the display substrate, wherein the TFT comprises a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode;
forming a plurality of power wirings in a non-display area of the display substrate surrounding the display area;
forming an insulating layer exposing at least a portion of the power wirings and having a plurality of contact holes;
forming a first electrode and an intermediate layer of an OLED in the display area;
forming a wiring electrode on the same layer as the first electrode in the non-display area; and
forming a second electrode of the OLED, wherein the second electrode is electrically connected to the power wirings and the wiring electrode.

15. The method of claim 14 , wherein the forming of the insulating layer comprises forming a stair gap between a portion in which the insulating layer is formed and a portion in which the insulating layer is not formed.

16. The method of claim 14 , wherein the insulating layer defines the contact holes, and wherein the forming of the wiring electrode comprises forming the wiring electrode over the insulating layer so as to electrically connect the wiring electrode to the exposed portion of the power wirings.

17. The method of claim 16 , wherein the insulating layer includes first and second insulating layers, wherein the first insulating layer includes an upper surface, a side surface, and a bottom surface formed between the first and second insulating layers, and wherein the wiring electrode is formed over the upper, side and bottom surfaces of the first insulating layer and the exposed portion of the power wirings.

18. The method of claim 14 , wherein the display area includes a plurality of pixels, wherein the intermediate layer comprises an organic emission layer and at least one pattern layer stacked on at least a surface of the organic emission layer, wherein the organic emission layer is formed in each of the pixels, and wherein the at least one pattern layer is formed over the display area and the non-display area.

19. The method of claim 18 , wherein the at least one pattern layer comprises at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer,
wherein the insulating layer includes first and second insulating layers, wherein the first insulating layer includes an upper surface, a side surface, and a bottom surface formed between the first and second insulating layers, wherein the at least one pattern layer is formed over the wiring electrode and the upper and bottom surfaces of the first insulating layer, and wherein the at least one pattern layer is

Assignees

• Samsung Display Co Ltd

Inventors

• You Chungi

Classifications

• H01L27/3276 Primary

  Electricity · mapped topic

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title