Nonvolatile semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9786678-B2
Application number	US-201514798891-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Sep 11, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer;
a semiconductor layer having the first direction as a longer direction;
a tunnel insulating layer contacting a side surface of the semiconductor layer;
a charge accumulation layer contacting a side surface of the tunnel insulating layer; and
a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer,
the charge accumulation layer including:
a first portion facing the conductive layer and extending in the first direction, and
a second portion facing the inter-layer insulating layer and extending in the first direction,

the first portion being thinner than the second portion, and
a film thickness of the second portion of the charge accumulation layer in a second direction crossing the first direction being approximately constant.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein the block insulating layer covers a side surface of the conductive layer, and does not cover an upper surface and a lower surface of the conductive layer.

3. The nonvolatile semiconductor memory device according to claim 1 , further comprising a stacked film covering the conductive layer, wherein the stacked film
contacts the inter-layer insulating layer at an upper surface and a lower surface, and
contacts the block insulating layer at a side surface facing the semiconductor layer.

4. The nonvolatile semiconductor memory device according to claim 3 , wherein
the stacked film comprises a high-k dielectric insulating layer, and
the high-k dielectric insulating layer includes a protruding portion protruding in the first direction, on an upper surface and a lower surface of the high-k dielectric insulating layer.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein the charge accumulation layer comprises:
a silicon nitride layer contacting the tunnel insulating layer; and
a silicon oxynitride layer contacting a portion facing the inter-layer insulating layer, of the silicon nitride layer.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein the inter-layer insulating layer contacts the charge accumulation layer.

7. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a stacked film covering the conductive layer, wherein the stacked film comprises a high-k dielectric insulating layer, and
an insulating layer contacting the high-k dielectric insulating layer and the inter-layer insulating layer is provided.

8. A method of manufacturing the nonvolatile semiconductor memory device according to claim 1 , comprising:
alternately stacking a plurality of inter-layer insulating layers and a plurality of first sacrifice layers;
forming a memory hole penetrating the plurality of inter-layer insulating layers and the plurality of first sacrifice layers;
sequentially forming the charge accumulation layer, the tunnel insulating layer, and the semiconductor layer on a sidewall of the memory hole;
removing the plurality of first sacrifice layers;
oxidizing part of the charge accumulation layer to form the block insulating layer; and
forming a conductive layer between the plurality of inter-layer insulating layers.

9. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8 , further comprising:
before forming the charge accumulation layer on the sidewall of the memory hole, forming a second sacrifice layer on the sidewall of the memory hole; and
after removing the first sacrifice layer and before oxidizing part of the charge accumulation layer to form the block insulating layer, removing the second sacrifice layer.

10. The method of manufacturing a nonvolatile semiconductor memory device according to claim 9 , further comprising:
after forming the block insulating layer and before forming the conductive layer, forming an additional block layer covering an upper surface and lower surface of the inter-layer insulating layer and a side surface of the block insulating layer.

11. The method of manufacturing a nonvolatile semiconductor memory device according to claim 10 , further comprising:
when removing the second sacrifice layer, removing the second sacrifice layer in a range larger than a width between two inter-layer insulating layers adjacent in a stacking direction; and
when forming the additional block layer, forming a high dielectric insulating layer covering the side surface of the block insulating layer.

12. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8 , further comprising
when forming the charge accumulation layer, sequentially forming a silicon oxynitride layer and a silicon nitride layer.

13. The method of manufacturing a nonvolatile semiconductor memory device according to claim 8 , further comprising:
after forming the memory hole, oxidizing the first sacrifice layer exposed inside the memory hole to form an oxide layer; and
forming the charge accumulation layer on a sidewall of the inter-layer insulating layer and a sidewall of the oxide layer.

14. A nonvolatile semiconductor memory device, comprising:
a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer;
a semiconductor layer having the first direction as a longer direction;
a tunnel insulating layer contacting a side surface of the semiconductor layer;
a charge accumulation layer contacting a side surface of the tunnel insulating layer; and
a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer,
the charge accumulation layer including:
a first portion facing the conductive layer and extending in the first direction; and
a second portion facing the inter-layer insulating layer and extending in the first direction,

the first portion being thinner than the second portion, and
a side surface of the second portion being flush with the first direction.

15. The nonvolatile semiconductor memory device according to claim 14 , wherein the block insulating layer covers a side surface of the conductive layer, and does not cover an upper surface and a lower surface of the conductive layer.

16. The nonvolatile semiconductor memory device according to claim 14 , further comprising a stacked film covering the conductive layer, wherein the stacked film:
contacts the inter-layer insulating layer at an upper surface and a lower surface, and
contacts the block insulating layer at a side surface facing the semiconductor layer.

17. The nonvolatile semiconductor memory device according to claim 16 , wherein
the stacked film comprises a high-k dielectric insulating layer, and
the high-k dielectric insulating layer includes a protruding portion protruding in the first direction, on an upper surface and a lower surface of the high-k dielectric insulating layer.

18. The nonvolatile semiconductor memory device according to claim 14 , wherein the charge accumulation layer comprises:
a silicon nitride layer contacting the tunnel insulating layer; and
a silicon oxynitride layer contacting a portion facing the inter-layer insulating layer, of the silicon nitride layer.

19. The nonvolatile semiconductor memory device according to claim 14 , wherein the inter-layer insulating layer contacts the charge accumulation layer.

Assignees

• Toshiba Memory Corp

Inventors

• Sekine Katsuyuki
• Higuchi Masaaki
• Shingu Masao
• Ishigaki Hirokazu
• Yasuda Naoki

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L29/518

  Electricity · mapped topic