Fabrication method of a stack of electronic devices

Patent metadata

Field	Value
Publication number	US-9786658-B2
Application number	US-201615388617-A
Country	US
Kind code	B2
Filing date	Dec 22, 2016
Priority date	Dec 22, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer; a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device; b) bombarding the polycrystalline semiconductor layer by a beam of species configured to form an amorphous part and to preserve a superficial polycrystalline part; c) bonding the first and second structures; d) removing the second substrate of the second structure; e) introducing dopants into the amorphous part, through the exposed active layer; f) thermally activating the dopants by recrystallization of the amorphous part.

First claim

The invention claimed is:

1. Fabrication method of a stack of electronic devices, comprising the following steps:
a) providing:
a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer;
a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device;

b) bombarding the polycrystalline semiconductor layer by a beam of species so as to form an amorphous part and to preserve a superficial polycrystalline part;
c) bonding the first and second structures by direct bonding between the first dielectric layer and the superficial polycrystalline part;
d) removing the second substrate of the second structure so as to expose the active layer;
e) introducing dopants into the amorphous part, through the exposed active layer so as to form a ground plane;
f) thermally activating the dopants introduced in step e) by recrystallization of the amorphous part.

2. Method according to claim 1 , wherein step b) is executed in such a way that the preserved superficial polycrystalline part forms a continuous film.

3. Method according to claim 1 , wherein step b) is executed in such a way that the preserved superficial polycrystalline part presents a suitable thickness to form a polycrystalline seed, the thickness preferably being comprised between 2 nm and 4 nm.

4. Method according to claim 1 , wherein the species of the beam are silicon atoms.

5. Method according to claim 1 , wherein step f) is executed with a pulsed laser.

6. Method according to claim 1 , wherein step f) is executed by applying a thermal annealing presenting:
an annealing temperature value lower than or equal to 600° C.
an anneal time value lower than or equal to 1 min.

7. Method according to claim 1 , wherein step e) is executed so as not to recrystallize the amorphous part.

8. Method according to claim 1 , wherein the polycrystalline semiconductor layer is silicon-based.

9. Method according to claim 1 , wherein the first dielectric layer is silicon dioxide-based, and presents a thickness of more than 60 nm, preferably more than 80 nm.

10. Method according to claim 1 , wherein the dopants introduced in step e) are selected from the group comprising B, In, P, and As.

11. Method according to claim 1 , comprising a step consisting in forming an oxide layer on the superficial polycrystalline part before step c), direct bonding taking place between the first dielectric layer and the oxide layer.

Assignees

• Commissariat à l'Energie Atomique et aux Energies Alternatives

Inventors

• Mathieu Benoit
• Fenouillet-Beranger Claire

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P30/208

  of electrically inactive species · CPC title