Semiconductor devices including a bit line structure and a contact plug

Patent metadata

Field	Value
Publication number	US-9786558-B2
Application number	US-201615189697-A
Country	US
Kind code	B2
Filing date	Jun 22, 2016
Priority date	Feb 7, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a bit line structure on a substrate;
forming a bit line spacer on a sidewall of the bit line structure;
forming a lower plug pad on the sidewall of the bit line structure, wherein the bit line spacer is between the bit line structure and the lower plug pad;
recessing an upper portion of the bit line structure and an upper portion of the bit line spacer; and
forming a upper plug pad on a recessed upper surface of the bit line structure and a recessed upper surface of the bit line spacer,
wherein the recessed upper surface of the bit line structure slopes downward toward the sidewall of the bit line structure, and
wherein the lower plug pad and the upper plug pad comprise respective portions of one contact plug.

2. The method of claim 1 , wherein forming the lower plug pad comprises:
forming a conductive layer on the sidewall of the bit line structure, wherein the bit line spacer is between the bit line structure and the conductive layer; and
removing an upper portion of the conductive layer to expose at least a portion of the bit line spacer.

3. The method of claim 2 , wherein forming the lower plug pad further comprises:
forming a first separation spacer on the at least the portion of the bit line spacer that is exposed by the removing;
forming a second separation spacer on the first separation spacer;
forming a molding pattern on the second separation spacer, the molding pattern exposing at least a portion of the second separation spacer;
removing the second separation spacer; and
removing the molding pattern and a portion of the conductive layer that is below the molding pattern.

4. The method of claim 3 , wherein the first separation spacer remains on the bit line spacer after the lower plug pad is formed.

5. The method of claim 4 , wherein recessing the upper portion of the bit line structure and the upper portion of the bit line spacer comprises:
removing the first separation spacer.

6. The method of claim 2 , further comprising:
before recessing the upper portion of the bit line structure and the upper portion of the bit line spacer;
sequentially forming a sacrificial barrier layer and a sacrificial upper plug conductive layer covering the at least the portion of the bit line spacer that is exposed by the removing;
forming an insulating pattern penetrating the sacrificial barrier layer and the sacrificial upper plug conductive layer by patterning the sacrificial barrier layer and the sacrificial upper plug conductive layer; and
removing the sacrificial barrier layer and the sacrificial upper plug conductive layer,
wherein the insulating pattern is formed on the sidewall of the bit line structure.

7. The method of claim 6 , wherein recessing the upper portion of the bit line structure and the upper portion of the bit line spacer comprises:
recessing portions of the bit line structure and the bit line spacer that are exposed by the insulating pattern.

8. The method of claim 1 , further comprising:
forming a plug barrier pattern extending along the recessed upper surface of the bit line structure and the recessed upper surface of the bit line spacer,
wherein the plug barrier pattern extends between the upper plug pad and the lower plug pad.

9. The method of claim 8 , wherein the upper plug pad, the lower plug pad, and the plug barrier pattern constitute a storage contact plug that is electrically connected to the substrate.

10. The method of claim 1 ,
wherein the bit line structure comprises a bit line electrode and a capping pattern sequentially stacked on the substrate, and
wherein recessing the upper portion of the bit line structure comprises recessing an upper portion of the capping pattern.

11. The method of claim 10 , wherein the upper plug pad is on a recessed upper surface of the capping pattern.

12. The method of claim 1 , further comprising forming an insulator directly on a first curved surface of the bit line structure, wherein recessing the upper portion of the bit line structure comprises forming a second curved surface of the bit line structure while the insulator is directly on the first curved surface of the bit line structure.

13. The method of claim 1 , further comprising forming an insulator that directly contacts a side surface of the bit line structure, wherein forming the upper plug pad comprises forming the upper plug pad adjacent a sidewall of the insulator.

14. The method of claim 1 , wherein an uppermost surface of the lower plug pad is exposed after recessing the upper portion of the bit line structure and the upper portion of the bit line spacer.

15. The method of claim 1 ,
wherein the upper and lower plug pads comprise conductive upper and lower plug pads, respectively, and
wherein forming the upper plug pad comprises forming the conductive upper plug pad to overlap a portion of the conductive lower plug pad.

16. The method of claim 1 , wherein forming the upper plug pad comprises forming the upper plug pad on the recessed upper surface of the bit line structure that slopes downward toward the sidewall of the bit line structure.

17. A method of forming a semiconductor device, the method comprising:
forming a bit line structure on a substrate;
forming an insulating material on a first portion of an upper region of the bit line structure adjacent a first side of the bit line structure;
recessing a second portion of the upper region of the bit line structure adjacent a second side of the bit line structure where the insulating material has not been formed; and
forming a storage contact plug on the second portion of the upper region of the bit line structure that is recessed, without forming the storage contact plug on the first portion of the upper region of the bit line structure that comprises the insulating material thereon.

18. A method of forming a semiconductor device, the method comprising:
forming first and second bit line structures that are laterally spaced apart from each other on a substrate;
forming an insulating material on a first upper surface of the first bit line structure, without forming the insulating material on a second upper surface of the first bit line structure;
recessing the second upper surface of the first bit line structure where the insulating material has not been formed; and
forming a storage contact plug on the second upper surface of the first bit line structure that is recessed, without forming the storage contact plug on the first upper surface of the first bit line structure that comprises the insulating material thereon.

19. The method of claim 18 , further comprising:
forming a conductive material between a sidewall of the first bit line structure and a sidewall of the second bit line structure; and
forming an opening in the conductive material that exposes the first upper surface of the bit line structure, before forming the insulating material,
wherein forming the insulating material comprises forming the insulating material in the opening in the conductive material.

20. The method of claim 19 , wherein recessing the second upper surface of the first bit line structure comprises recessing the conductive material, after forming the insulating material in the opening in the conductive material.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Eun
• Jeong Hoon
• Kim Jae-Hyun
• Lee Dong-Won
• Han Jung-Gu
• Hwang Ji-Hye

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title