Self aligned conductive lines

Patent metadata

Field	Value
Publication number	US-9786554-B1
Application number	US-201615176284-A
Country	US
Kind code	B1
Filing date	Jun 8, 2016
Priority date	Jun 8, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.

First claim

What is claimed is:

1. A method for forming conductive lines on a semiconductor wafer, the method comprising:
forming a first hardmask on an insulator layer, a planarizing layer on the first hardmask, a second hardmask on the planarizing layer and a layer of sacrificial mandrel material on the second hardmask;
patterning a mask on the layer of sacrificial material;
removing a portion of the mask;
removing exposed portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first sacrificial mandrel and a second sacrificial mandrel on the second hardmask, wherein the first sacrificial mandrel has a gap defined by a first portion of the first sacrificial mandrel and a second portion of the first sacrificial mandrel;
depositing a filler material on the second hardmask between the first sacrificial mandrel and the second sacrificial mandrel;
removing a portion of the filler material between the first sacrificial mandrel and the second sacrificial mandrel to expose a portion of the second hardmask;
removing an exposed portion of the second hardmask and an exposed portion of the planarizing layer to form a cavity that exposes a portion of the first hardmask;
removing the filler material;
depositing a layer of spacer material in the gap, the cavity, and over exposed portions of the first sacrificial mandrel, the second sacrificial mandrel and the first hardmask;
removing portions of the layer of spacer material to form spacers adjacent to the first sacrificial mandrel and the second sacrificial mandrel, and expose portions of the second hardmask;
removing exposed portions of the second hardmask, the planarizing layer and the first hardmask to expose portions of the insulator layer;
removing the second hardmask, the spacers, and the planarizing layer;
removing exposed portions of the insulator layer to form a trench in the insulator layer; and
filling the trench with a conductive material.

2. The method of claim 1 , wherein the method further comprises depositing a liner layer in the trench prior to depositing the conductive material.

3. The method of claim 1 , wherein the trench defines a conductive line.

4. The method of claim 1 , wherein the sacrificial mandrel material, the spacers and the filler material are dissimilar materials.

5. The method of claim 1 , wherein the spacers are formed from an oxide material.

6. The method of claim 1 , wherein the layer of sacrificial mandrel material includes a semiconductor material.

7. The method of claim 1 , wherein the filler material includes a flowable carbide material.

Assignees

• IBM

Inventors

• Burns Sean D
• Clevenger Lawrence A
• Desilva Anuja E
• Felix Nelson M
• Kanakasabapathy Sivananda K
• Mignot Yann A M
• Penny Christopher J
• Quon Roger A
• Saulnier Nicole A

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title