Etch damage and ESL free dual damascene metal interconnect

Patent metadata

Field	Value
Publication number	US-9786549-B2
Application number	US-201615083484-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Jun 19, 2012
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

First claim

The invention claimed is:

1. A semiconductor device manufacturing process, comprising:
providing a substrate;
forming a first dielectric layer over the substrate;
patterning a via opening in the first dielectric layer;
forming a sacrificial layer over the first dielectric layer;
patterning a trench opening through the sacrificial layer;
filling the via opening and trench opening with conductive material;
removing the sacrificial layer; and
forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a lower dielectric constant than the first dielectric layer.

2. The process of claim 1 , wherein when the sacrificial layer is removed, the conductive material in the trench opening remains to protrude above an upper surface of the first dielectric layer, and the second dielectric layer is formed about sidewalls of the protrusion of conductive material.

3. The process of claim 1 , wherein the via opening is etched through the first dielectric layer before forming the sacrificial layer.

4. The process of claim 3 , wherein:
the forming of the sacrificial layer fills the via opening with material of the sacrificial layer; and
the trench is etched in a chamber and the sacrificial layer is removed from the via opening by further etching in the chamber prior to removing the substrate from the chamber.

5. The process of claim 1 , wherein the second dielectric layer is formed by a non-conformal deposition process that leaves air gaps in the second dielectric layer.

6. The process of claim 1 , wherein the first dielectric layer has an effective dielectric constant greater than 2.1 and less than 3.5 and the second dielectric layer has an effective dielectric constant less than 2.1.

7. The semiconductor device manufacturing process of claim 1 , wherein the first dielectric layer has a porosity less than 20% and the second dielectric layer has a porosity greater than 20%.

8. A semiconductor device manufacturing process, comprising:
providing a substrate;
forming a first dielectric layer over the substrate;
forming a via opening in the first dielectric layer;
forming a sacrificial layer having an upper portion which extends over the first dielectric layer and having a lower portion which fills the via opening;
removing a first selected portion of the sacrificial layer to form a trench opening in the upper portion of the sacrificial layer;
removing a second selected portion of the sacrificial layer to form a re-opened via opening in the lower portion of the sacrificial layer;
filling the re-opened via opening with conductive material to form a conductive via and filling the trench opening to form a conductive trench;
removing a remaining portion of the sacrificial layer while leaving the conductive trench and conductive via in place; and
forming a second dielectric layer over the first dielectric layer and along a sidewall of the conductive trench.

9. The process of claim 8 , wherein the second dielectric layer has a different dielectric constant than the first dielectric layer.

10. The process of claim 8 , wherein the first dielectric layer is a low-k dielectric layer, and the second dielectric layer is an extreme low-k dielectric layer.

11. The process of claim 8 , when the second dielectric layer is deposited by a non-conformal deposition process.

12. The process of claim 8 , wherein the first dielectric layer has an effective dielectric constant greater than 2.1 and the second dielectric layer has an effective dielectric constant less than 2.1.

13. The process of claim 8 , wherein the first dielectric layer has a lower porosity than the second dielectric layer.

14. The process of claim 8 , wherein the first dielectric layer is formed without air gaps and the second dielectric layer is formed with air gaps.

15. The process of claim 8 , wherein the sacrificial layer comprises amorphous carbon.

16. The process of claim 8 , wherein the first dielectric layer is an organosilicate glass.

17. The process of claim 8 , wherein the trench opening is patterned by plasma etching with an etch gas comprising NH 3 or a combination of N 2 and H 2 .

18. The process of claim 8 , wherein the removing of the sacrificial layer comprises etching with etch conditions that remove the material that makes up the sacrificial layer preferentially with respect to the material that makes up the first dielectric layer.

19. The semiconductor device manufacturing process of claim 8 , wherein the first dielectric layer has a porosity less than 20% and the second dielectric layer has a porosity greater than 20%.

20. A method of forming a dual damascene copper interconnect structure, comprising:
depositing a first dielectric layer over a substrate;
depositing a sacrificial layer over the first dielectric layer;
etching trenches that extend through the sacrificial layer, but not through the first dielectric layer;
etching vias through the first dielectric layer, before or after at least one of the deposition of the sacrificial layer or the etching of the trenches;
depositing a conductive material to fill the trenches and the vias and form a damascene structure comprising conductive material-filled vias in a field of the first dielectric layer and conductive material-filled trenches in a field of the sacrificial layer material;
removing the sacrificial layer; and
depositing a second dielectric layer to form a damascene structure comprising copper-filled vias in the field of the first dielectric layer and conductive material-filled trenches in a field of the second dielectric layer,
wherein the first dielectric layer has a porosity less than 20% and the second dielectric layer has a porosity greater than 20%.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Singh Sunil Kumar
• Lee Chung-Ju
• Bao Tien-I

Classifications

• H10W20/0888

  wherein via-level dielectrics are compositionally different than trench-level dielectrics · CPC title

• H10W20/0886

  involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric · CPC title

• H10W20/0884

  involving forming vias by burying sacrificial pillars in the dielectric parts and removing the pillars · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/076

  in via holes or trenches · CPC title