Polycrystalline semiconductor layer and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9786500-B2
Application number	US-201515038350-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	May 15, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The present application discloses a method of fabricating a polycrystalline semiconductor layer, comprising forming a heat storage layer; forming a buffer layer on the heat storage layer; forming a first amorphous semiconductor layer on a side of the buffer layer distal to the heat storage layer; and crystallizing the first amorphous semiconductor layer to form a first polycrystalline semiconductor layer.

First claim

What is claimed is:

1. A method of fabricating a polycrystalline semiconductor layer, comprising:
forming a heat storage layer;
forming a buffer layer on the heat storage layer;
forming a first amorphous semiconductor layer on a side of the buffer layer distal to the heat storage layer; and
crystallizing the first amorphous semiconductor layer to form a first polycrystalline semiconductor layer;
wherein crystallizing the first amorphous semiconductor layer comprises at least partially melting both the first amorphous semiconductor layer and the heat storage layer in a single crystallization process; and
solidifying both the first amorphous semiconductor layer and the heat storage layer.

2. The method of claim 1 , wherein the first amorphous semiconductor layer comprises amorphous silicon, and the first polycrystalline semiconductor layer comprises polysilicon.

3. The method of claim 1 , wherein the crystallizing step is performed using excimer laser annealing.

4. The method of claim 1 , wherein the heat storage layer is a second amorphous semiconductor layer; and
the heat storage layer is at least partially crystallized during solidifying.

5. The method of claim 4 , wherein the second amorphous semiconductor layer comprises amorphous silicon.

6. The method of claim 3 , wherein the excimer laser annealing is performed under the following conditions: a laser pulse frequency of about 100 Hz to about 400 Hz, an overlapping ratio of about 90% to about 98%, a laser pulse width less than 100 ns, and a laser energy density of about 100 mJ/cm 2 to about 600 mJ/cm 2 .

7. The method of claim 2 , wherein the thickness of the first amorphous semiconductor layer is in the range of about 40 nm to about 60 nm.

8. The method of claim 4 , wherein the thickness of the heat storage layer is in the range of about 20 nm to about 30 nm.

9. The method of claim 1 , wherein the thickness of the buffer layer is in the range of about 2000 Å to about 5000 Å.

10. The method of claim 1 , further comprising:
dehydrogenating the first amorphous semiconductor layer prior to the step of crystallizing the first amorphous semiconductor layer.

11. The method of claim 1 , further comprising:
forming an ancillary buffer layer;
wherein the heat storage layer is formed on a side of the ancillary buffer layer proximal to the buffer layer.

12. The method of claim 11 , wherein the thickness of the ancillary buffer layer is in the range of about 2000 Å to about 5000 Å.

13. The method of claim 1 , further comprising providing a base substrate, wherein the heat storage layer is formed on the base substrate.

14. A polycrystalline semiconductor layer fabricated by a method of claim 1 .

15. A thin film transistor fabricated from a polycrystalline semiconductor layer of claim 14 .

16. An array substrate comprising a thin film transistor of claim 15 .

17. A display device comprising an array substrate of claim 16 .

18. The method of claim 4 , wherein protrusions are formed between neighboring crystals of the heat storage layer during melting and solidifying of the heat storage layer; and
heights of the protrusions are approximately the same as a thickness of the heat storage layer.

19. A semiconductor device comprising a first polycrystalline semiconductor layer, a second polycrystalline semiconductor layer, and a buffer layer sandwiched by the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer; wherein the first polycrystalline semiconductor layer having an average grain size of no less than 375 nm; and the second polycrystalline semiconductor layer comprises protrusions between neighboring crystals, the heights of which are approximately the same as the thickness of the second polycrystalline semiconductor layer.

20. The semiconductor device of claim 19 , wherein the thickness of the second polycrystalline semiconductor layer is in the range of about 20 nm to about 30 nm.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Xu Wenqing
• Tian Hongwei
• Long Chunping

Classifications

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title