Memory system

Patent metadata

Field	Value
Publication number	US-9786389-B2
Application number	US-201615291862-A
Country	US
Kind code	B2
Filing date	Oct 12, 2016
Priority date	Oct 16, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a first memory device including a first memory having a first latency and a first memory controller suitable for controlling the first memory to store data, the first memory device maintaining information of the first latency;
a second memory device including a second memory having a second latency different from the first latency and a second memory controller suitable for controlling the second memory to store data, the second memory device maintaining information of the second latency; and
a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices, accessing the second memory device through the first memory device, and communicating with each of the first and second memories according to the information of the first and second latencies provided from the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the processor communicates with the first memory during the second latency for a communication with the second memory, and
wherein the second memory device includes:
a stacked memory cell array including a plurality of stacked memory cell layers, the respective stacked memory cell layers including a plurality of memory cell groups and/or a plurality of redundancy memory cell groups; and
a repair control circuit suitable for performing a repair operation to replace a defective memory cell group among the plurality of memory cell groups with one among the plurality of redundancy memory cell groups.

2. The memory system of claim 1 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

3. The memory system of claim 1 , wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

4. The memory system of claim 1 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

5. The memory system of claim 1 , wherein the first memory device is a volatile memory device.

6. The memory system of claim 1 , wherein the second memory device is a non-volatile memory device.

7. The memory system of claim 6 , wherein the non-volatile memory device is a non-volatile random access memory device.

8. The memory system of claim 1 ,
wherein the stacked memory cell layers includes at least one first memory cell layer and at least one second memory cell layer,
wherein the at least one first memory cell layer includes the plurality of memory cell groups, and
wherein the at least one second memory cell layer includes the plurality of redundancy memory cell groups.

9. The memory system of claim 8 ,
wherein the repair control circuit performs the repair operation to the defective memory cell group by replacing the defective memory cell group of the first memory cell layer with the redundancy memory cell group of the second memory cell layer, and
wherein the defective memory cell group and the redundancy memory cell group correspond to the same block address.

10. The memory system of claim 9 ,
wherein the repair control circuit includes a fuse unit coupled to the redundancy memory cell groups, and
wherein the fuse unit includes:
an enable fuse suitable for enabling the fuse unit;
a layer address fuse suitable for storing a layer address corresponding to the first memory cell layer having the defective memory cell group; and
an address fuse suitable for storing a fail address corresponding to the defective memory cell group.

11. The memory system of claim 1 , wherein the stacked memory cell array has a cross point structure.

12. The memory system of claim 1 ,
wherein each of the plurality of memory cell groups includes a plurality of memory cells defined at intersections of a plurality of first conductive lines extending in a first direction and a plurality of second conductive lines extending in a second direction,
wherein each of the plurality of redundancy memory cell groups includes a plurality of redundancy memory cells defined at intersections of a plurality of third conductive lines extending in the first direction and a plurality of fourth conductive lines extending in the second direction.

13. The memory system of claim 12 , wherein the repair control circuit performs the repair operation by changing one of the plurality of second conductive lines coupled to a defective memory cell among the plurality of memory cells to one of the plurality of fourth conductive lines.

14. The memory system of claim 13 , wherein the repair control circuit performs the repair operation by changing one or more of the plurality of first and second conductive lines coupled to one or more defective memory cells among the plurality of memory cells in a first memory cell layer among the plurality of memory cell layers to one or more of the plurality of third and fourth conductive lines coupled to one or more among the plurality of redundancy memory cells in a second memory cell layer among the plurality of memory cell layers.

15. A memory system comprising:
a first memory device including a first memory having a first latency and a first memory controller suitable for controlling the first memory to store data, the first memory device maintaining information of the first latency;
a second memory device including a second memory having a second latency different from the first latency and a second memory controller suitable for controlling the second memory to store data, the second memory device maintaining information of the second latency; and
a processor suitable for accessing the first memory, accessing the second memory through the first memory device, and communicating with each of the first and second memories according to the information of the first and second latencies provided from the first and second memory devices,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the processor communicates with the first memory during the second latency for a communication with the second memory, and
wherein the second memory device includes:
a stacked memory cell array including a plurality of stacked memory cell layers, the respective stacked memory cell layers including a plurality of memory cell groups and/or a plurality of redundancy memory cell groups; and
a repair control circuit suitable for performing a repair operation to replace a defective memory cell group among the plurality of memory cell groups with one among the plurality of redundancy memory cell groups.

16. The memory system of claim 15 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

17. The memory system of claim 15 , wherein the value of the handshaking information field indicates the signal as one of a data request signa

Assignees

• Sk Hynix Inc

Inventors

• Jung Hoe-Kwon
• Kim Min-Chang
• Kim Chang-Hyun
• Lee Do-Yun
• Lee Yong-Woo
• Lee Jae-Jin

Classifications

• G11C29/70 Primary

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G06F3/0622

  in relation to access · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G11C29/4401

  for self repair · CPC title