Shift register unit and control method thereof, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-9786228-B2
Application number	US-201615321035-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	May 22, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A shift register unit and a control method thereof, a gate driving circuit, and a display device. The shift register unit includes a signal input module, connected to a signal input terminal, a first clock signal terminal and a control node; a pull-down module, connected to the control node, a first voltage terminal and a signal output terminal; a first pull-up control module, connected to the control node, the pull-up module and a second voltage terminal; a second pull-up control module, connected to the control node, the pull-up module, the first clock signal terminal, the first voltage terminal and a second clock signal terminal; and a pull-up module, connected to the signal output terminal and the second voltage terminal. The problem that it is difficult to realize a narrow display frame by the bonding process due to size increase of the driving circuit can be solved.

First claim

What is claimed is:

1. A shift register unit, comprising a signal input module, a pull-down module, a pull-up module, a first pull-up control module and a second pull-up control module;
the signal input module being connected to a signal input terminal, a first clock signal terminal and a control node, respectively, and configured to be enabled under control of the first clock signal terminal so as to output a signal of the signal input terminal to the control node;
the pull-down module being connected to the control node, a first voltage terminal and a signal output terminal, respectively, and configured to output a signal of the first voltage terminal to the signal output terminal under control of the control node, store a voltage level of the control node in a state where the signal input module is enabled, and maintain the voltage level of the control node in a state where the signal input module is disabled;
the first pull-up control module being connected to the control node, the pull-up module and a second voltage terminal, respectively, and configured to output a signal of the second voltage terminal, as a disabling signal, to the pull-up module under control of the control node;
the second pull-up control module being connected to the control node, the pull-up module, the first clock signal terminal, the first voltage terminal and a second clock signal terminal, respectively, and configured to output the signal of the first voltage terminal, as an enabling signal, to the pull-up module under control of the control node, the first clock signal terminal and the second clock signal terminal; and
the pull-up module being further connected to the signal output terminal and the second voltage terminal, and configured to be in a disabled state under control of the disabling signal outputted by the first pull-up control module or be in an enabled state under control of the enabling signal outputted by the second pull-up control module so as to output the signal of the second voltage terminal to the signal output terminal.

2. The shift register unit according to claim 1 , wherein the first pull-up control module outputs the disabling signal during a first time period, the second pull-up control module outputs the enabling signal during a second time period, the first time period and the second time period do not overlap with each other,
the pull-up module is in the disabled state during the first time period, whereas the pull-up module is in the enabled state and outputs the signal of the second voltage terminal to the signal output terminal during the second time period.

3. The shift register unit according to claim 2 , wherein the second pull-up control module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, as well as a second capacitor and a third capacitor;
a gate of the fifth transistor being connected to the control node, a first electrode of the fifth transistor being connected to the first clock signal terminal, and a second electrode of the fifth transistor being connected to a first electrode of the sixth transistor;
a gate of the sixth transistor being connected to the first dock signal terminal, and a second electrode of the sixth transistor being connected to the first voltage terminal;
a gate of the seventh transistor being connected to the second dock signal terminal, a first electrode of the seventh transistor being connected to the pull-up module, and a second electrode of the seventh transistor being connected to a first electrode of the eighth transistor;
a gate of the eighth transistor being connected to the first electrode of the sixth transistor, and a second electrode of the eighth transistor being connected to the first voltage terminal;
a first terminal of the second capacitor being connected to the second clock signal terminal, and a second terminal of the second capacitor being connected to the first electrode of the seventh transistor;
a first terminal of the third capacitor being connected to the first electrode of the sixth transistor, and a second terminal of the third capacitor being connected to the gate of the seventh transistor.

4. A gate driving circuit comprising shift register units according to claim 2 and cascaded in at least two stages, wherein
the signal input terminal of the shift register unit in a first stage is connected to a trigger signal terminal;
except the shift register unit in the first stage, the signal input terminal of the shift register unit in each of the rest stages is connected to the signal output terminal of the shift register unit in an adjacently upper stage.

5. A driving method for driving the shift register unit according to claim 2 , comprising that:
a trigger signal is inputted to the signal input terminal, the signal input module is enabled under control of the first clock control terminal to transmit the trigger signal to the control node, so that the pull-down module is disabled and the first pull-up control module is disabled, the pull-down module stores the voltage level of the control node, the second pull-up control module does not output the enabling signal to the pull-up module under control of the second clock control terminal, the pull-up module is disabled, the signal output terminal outputs a non-scanning signal;
the trigger signal is inputted to the signal input terminal, the signal input module is disabled under control of the first clock control terminal, the pull-down module maintains the voltage level of the control node, so that the pull-down module is disabled and the first pull-up control module is disabled, the second pull-up control module outputs the enabling signal to the pull-up module under control of the second clock control terminal, so that the pull-up module is enabled, the signal output terminal outputs a scanning signal;
the trigger signal is inputted to the signal input terminal, the signal input module is enabled under control of the first dock control terminal to transmit the scanning signal to the control node, so that the pull-down module is disabled and the first pull-up control module is disabled, the pull-down module stores the voltage level of the control node, the output terminal of the second pull-up control module continues to output the enabling signal under control of the second dock control terminal, so that the pull-up module maintains being enabled, the signal output terminal outputs the scanning signal;
a non-trigger signal is inputted to the signal input terminal, the signal input module is disabled under control of the first clock control terminal, the pull-down module maintains a voltage level of the control node, so that the pull-down module is disabled and the first pull-up control module is disabled, the second pull-up control module outputs the enabling signal to the pull-up module under control of the second dock control terminal, so that the pull-up module is enabled, the signal output terminal outputs the scanning signal;
the non-trigger signal is inputted to the signal input terminal, the signal input module is enabled under control of the first dock control terminal to transmit the non-trigger signal to the control node, so that the pull-down module is enabled and the first pull-up control module is enabled, the pull-down module stores the voltage level of the control node, the first pull-up control module outputs the disabling signal to the pull-up module, the second pull-up control module does not output the enabling signal to the pull-up module under control of the second clock control terminal, the pull-up module is disabled, the signal output terminal outputs the non-scanning signal; and
the non-trigger signal is inputted to the signal input terminal, the signal input module is disabled under control of the first dock control term

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ma Zhanjie

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title