Employing offsets to create multiple orthogonal channel sequences in frequency hopping systems

US9786155B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9786155-B2
Application numberUS-201615008088-A
CountryUS
Kind codeB2
Filing dateJan 27, 2016
Priority dateJan 27, 2016
Publication dateOct 10, 2017
Grant dateOct 10, 2017

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A system is provided that includes a control panel of a security system, a memory of the security system having a reference frequency hopping pattern and a reference frequency offset saved therein, a plurality of wireless threat sensors that communicate with the control panel using the reference frequency hopping pattern and a fixed frequency offset for each frequency and each hop of the reference frequency hop pattern, wherein the fixed frequency offset is an integer multiple of the reference frequency offset, and a processor of the security system that detects any nearby security systems that use the reference frequency hopping pattern, determines the integer multiple of the reference frequency offset used by each of the nearby security systems, and sets the fixed frequency offset used by the plurality of sensors at a selected integer multiple of the reference frequency offset that is not used by any nearby security system.

First claim

Opening claim text (preview).

The invention claimed is: 1. An apparatus comprising: a control panel of a security system that detects threats within a secured geographic area; a memory of the security system having a reference frequency hopping pattern and a reference frequency offset saved therein; a plurality of threat sensors of the security system located within the secured geographic area that communicate with the control panel using a modified frequency hopping pattern; and a processor of the security system that detects any nearby security systems that use any integer multiple variant of the reference frequency hopping pattern and that determines respective integer multiples of the reference frequency offset used by each of the nearby security systems, and wherein the processor of the security system determines a subsequent integer multiple different than the respective integer multiples, and wherein the processor of the security system sets the modified frequency hopping pattern by adding a product of the reference frequency offset and the subsequent integer multiple to each frequency of the reference frequency hopping pattern. 2. The apparatus as in claim 1 further comprising a processor of the control panel that transmits a beacon that synchronizes each of the plurality of threat sensors with the control panel. 3. The apparatus as in claim 1 further comprising a processor of a first threat sensor of the plurality of threat sensors that transmits a beacon that synchronizes each of the plurality of threat sensors with the first threat sensor. 4. The apparatus as in claim 3 further comprising a processor of the control panel that incorporates an identifier of the reference frequency hopping pattern and the subsequent integer multiple into the beacon. 5. The apparatus as in claim 2 further comprising a timing file saved within the memory that defines a repeating superframe, wherein the beacon synchronizes each of the plurality of threat sensors to a reference location within the superframe. 6. The apparatus as in claim 5 wherein the control panel and the plurality of threat sensors further comprise a time division multiple access communication system. 7. The apparatus as in claim 1 wherein the processor of the security system determines the subsequent integer multiple to be zero when no nearby security systems are found that are using any integer multiple variant of the reference frequency hopping pattern. 8. The apparatus as in claim 1 wherein the processor of the security system determines a highest relative integer value of the respective integer multiples. 9. The apparatus as in claim 8 wherein the processor of the security system determines the subsequent integer multiple by adding a value of one to the highest relative integer value. 10. The apparatus as in claim 1 wherein the reference frequency offset includes a channel spacing. 11. An apparatus comprising: a plurality of security systems, wherein each of the plurality of security systems detects threats within a respective secured geographic area; a respective control panel of each of the plurality of security systems, wherein the respective control panel of each of the plurality of security systems is located within the respective secured geographic area; a respective memory of the respective control panel of each of the plurality of security systems, wherein the respective memory of the respective control panel of each of the plurality of security systems includes an identical reference frequency hopping pattern and an identical reference frequency offset saved therein; a respective plurality of sensors of the respective secured geographic area of each of the plurality of security systems that detect the threats and that communicate with the respective control panel of each of the plurality of security systems using a respective modified frequency hopping pattern; and a respective processor of each of the plurality of security systems that detects any nearby security systems of the plurality of security systems that use an integer multiple variant of the identical reference frequency hopping pattern, determines respective integer multiples of the identical reference frequency offset used by each of the nearby security systems, determines a respective subsequent integer multiple different than the respective integer multiples, and sets the respective modified frequency hopping pattern by adding a product of the identical reference frequency offset and the respective subsequent integer multiple to each frequency of the identical reference frequency hopping pattern. 12. The apparatus as in claim 11 further comprising a respective processor of the respective control panel of each of the plurality of security systems that listens for a beacon transmitted by a master security system of the plurality of security systems and that synchronizes a respective one of the plurality of security systems to the master security system. 13. The apparatus as in claim 11 further comprising a respective processor of the respective control panel of one of the plurality of security systems transmitting a beacon that synchronizes each of the respective plurality of sensors with the respective control panel of the one of the plurality of security systems. 14. The apparatus as in claim 13 wherein the respective processor of the respective control panel of the one of the plurality of security systems incorporates an identifier of the identical reference frequency hopping pattern and the respective subsequent integer multiple into the beacon. 15. The apparatus as in claim 11 further comprising a respective processor of a first sensor of the respective plurality of sensors transmitting a beacon that synchronizes each of the respective plurality of sensors with the first sensor. 16. The apparatus as in claim 15 wherein each of the respective plurality of sensors includes a respective mesh network. 17. The apparatus as in claim 16 wherein the respective mesh network of each of the respective plurality of sensors includes a respective repeating superframe, and wherein the beacon synchronizes the respective mesh network of each of the respective plurality of sensors to a respective reference location within the respective repeating superframe. 18. The apparatus as in claim 11 wherein the respective processor of each of the plurality of security systems determines the respective subsequent integer multiple to be zero when no nearby security systems are found using any integer multiple variant of the identical reference frequency hopping pattern. 19. The apparatus as in claim 11 wherein the respective processor of each of the plurality of security systems determines a highest relative integer value of the respective integer multiples. 20. The apparatus as in claim 19 wherein the respective processor of each of the plurality of security systems determines the respective subsequent integer multiple by adding a value of one to the highest relative integer value. 21. An apparatus comprising: a plurality of security systems, wherein each of the plurality of security systems detects threats within a respective secured geographic area; a respective control panel of each of the plurality of security systems, wherein the respective control panel is located within the respective secured geographic area; a respective memory of the respective control panel of each of the plurality of security systems having an identical reference frequency hopping pattern and an identical reference freque

Assignees

Inventors

Classifications

  • G08B25/10Primary

    using wireless transmission systems {(G08B25/009 takes precedence)} · CPC title

  • using frequency hopping · CPC title

  • Central alarm receiver or annunciator arrangements · CPC title

  • Arrangements for sequence synchronisation · CPC title

  • with means for preventing interference · CPC title

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What does patent US9786155B2 cover?
A system is provided that includes a control panel of a security system, a memory of the security system having a reference frequency hopping pattern and a reference frequency offset saved therein, a plurality of wireless threat sensors that communicate with the control panel using the reference frequency hopping pattern and a fixed frequency offset for each frequency and each hop of the refere…
Who is the assignee on this patent?
Honeywell Int Inc
What technology area does this patent fall under?
Primary CPC classification G08B25/10. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).