Parallel incremental global routing

Patent metadata

Field	Value
Publication number	US-9785735-B1
Application number	US-201615290279-A
Country	US
Kind code	B1
Filing date	Oct 11, 2016
Priority date	Oct 11, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A system and method perform global routing during integrated circuit fabrication. The method includes performing a design change in a portion of an integrated circuit design using a processor, determining whether the design change requires rerouting, and requesting a global routing lock based on determining that the design change requires the rerouting. The method also includes a router providing control of the global routing lock to one of two or more of the threads that request the global routing lock, and performing global routing for all of the two or more of the threads in parallel. A physical implementation of the integrated circuit design is obtained.

First claim

What is claimed is:

1. A computer-implemented method of performing global routing during integrated circuit fabrication, the method comprising:
performing a design change in a portion of an integrated circuit design as a thread using a processor, wherein each of two or more of the threads operates on a respective one of the portions of the integrated circuit design;
determining using the processor, whether the design change requires rerouting;
requesting, using the processor, a global routing lock based on the determining indicating that the design change requires the rerouting, wherein the global routing lock maintains a network list for every portion of the integrated circuit design as static;
providing, using a router, control of the global routing lock to one of the two or more of the threads that request the global routing lock;
performing, using the router, global routing for all of the two or more of the threads in parallel during the control of the global routing lock by the one of the two or more of the threads and updating the network list based on the global routing for all of the two or more of the threads with consideration of all modifications of the network list for all of the two or more of the threads; and
fabricating a physical implementation of the integrated circuit design based on the global routing.

2. The method according to claim 1 , further comprising performing timing analysis for the portion of the integrated circuit design to determine the design change.

3. The method according to claim 1 , further comprising updating timing values based on the determining indicating that the design change does not require rerouting.

4. The method according to claim 1 , further comprising determining, using the processor, whether the global routing for the design change is completed upon obtaining the control of the global routing lock.

5. The method according to claim 4 , further comprising releasing the global routing lock without the router performing the global routing again based on the determining that the global routing is completed.

6. The method according to claim 5 , further comprising updating timing values following the releasing the global routing lock.

7. The method according to claim 1 , further comprising performing the design change using another processor associated with another portion of the integrated circuit design simultaneously with the performing the global routing using the router.

8. A system to perform global routing during integrated circuit fabrication, the system comprising:
a processor configured to perform a design change in a portion of an integrated circuit design as a thread, wherein each of two or more of the threads operates on a respective one of the portions of the integrated circuit design, determine whether the design change requires rerouting, and request a global routing lock based on determining that the design change requires the rerouting, wherein the global routing lock maintains a network list for every portion of the integrated circuit design as static; and
a router configured to provide control of the global routing lock to one of two or more of the threads that request the global routing lock, and perform global routing for the design changes of all of the two or more of the processors in parallel during the control of the global routing lock by the one of the two or more of the threads and updating the network list based on the global routing for all of the two or more of the threads with consideration of all modifications of the network list for all of the two or more of the threads, wherein, based on the global routing, the integrated circuit design is provided to fabricate a physical implementation of the integrated circuit design.

9. The system according to claim 8 , wherein the processor performs timing analysis for the portion of the integrated circuit design to determine the design change.

10. The system according to claim 8 , wherein the processor updates timing values based on determining that the design change does not require rerouting.

11. The system according to claim 8 , wherein the processor determine whether the global routing for the design change is completed upon obtaining the control of the global routing lock.

12. The system according to claim 11 , wherein the processor releases the global routing lock without the router performing the global routing again based on determining that the global routing is completed.

13. The system according to claim 12 , wherein the processor updates timing values following releasing the global routing lock.

14. The system according to claim 8 , further comprising another processor associated with another portion of the integrated circuit configured to perform a design change simultaneously with the router performing the global routing.

15. A computer program product for performing design of a portion of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to perform a method comprising:
performing a design change in the portion of an integrated circuit design as a thread, wherein each of two or more of the threads operates on a respective one of the portions of the integrated circuit design;
determining whether the design change requires rerouting;
requesting, from a router, a global routing lock based on the determining indicating that the design change requires the rerouting, wherein the global routing lock maintains a network list for every portion of the integrated circuit design as static; and
determining, upon obtaining the global routing lock, whether global routing for the design change was completed by the router during control of the global routing lock by another thread associated with another portion of the integrated circuit design, wherein, based on the global routing, the integrated circuit design is provided for physical implementation.

16. The computer program product according to claim 15 , further comprising performing timing analysis to determine the design change.

17. The computer program product according to claim 15 , further comprising releasing the global routing lock based on determining that the global routing for the design change was completed by the router.

18. The computer program product according to claim 17 , further comprising updating timing values based on the releasing the global routing lock.

19. The computer program product according to claim 15 , further comprising updating timing values based on the determining that the design change does not require rerouting.

20. The computer program product according to claim 15 , wherein the performing the design change is done simultaneously with the router performing the global routing for another design change associated with another portion of the integrated circuit design.

Assignees

• IBM

Inventors

• Campbell Paul M
• Hieter Nathaniel D
• Keller Douglas
• Matheny Adam P
• Suess Alexander J

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5077 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic