System and method for reducing cross coupling effects

Patent metadata

Field	Value
Publication number	US-9785601-B2
Application number	US-201615045282-A
Country	US
Kind code	B2
Filing date	Feb 17, 2016
Priority date	Sep 23, 2011
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.

First claim

What is claimed is:

1. A device comprising:
a first driver circuit coupled to a first bus line, wherein the first driver circuit includes a first delay element configured to:
receive a first input signal; and
generate a first output signal based on the first input signal, wherein the first output signal transitions logic levels after a first delay period responsive to the first input signal transitioning from a logic high level to a logic low level, wherein the first output signal transitions logic levels after a second delay period responsive to the first input signal transitioning from the logic low level to the logic high level, wherein the first delay element includes a sense amplifier that includes cross-coupled NAND gates, and wherein the first driver circuit is configured to transmit the first output signal over the first bus line; and

a second driver circuit coupled to a second bus line, wherein the second driver circuit is configured to transmit a second output signal over the second bus line.

2. The device of claim 1 , wherein the second bus line is in close physical proximity to the first bus line, and wherein the first driver circuit, the second driver circuit, the first bus line, and the second bus line are included in a mobile device.

3. The device of claim 1 , wherein the sense amplifier comprises a first pair of precharge p-type metal oxide semiconductor (PMOS) transistors, wherein a first PMOS transistor of the first pair of precharge PMOS transistors is configured to pull up a voltage at a terminal of a first n-type metal oxide semiconductor (NMOS) transistor and a terminal of a second NMOS transistor, and wherein a second PMOS transistor of the first pair of precharge PMOS transistors is configured to pull up a voltage at a terminal of a third NMOS transistor and a terminal of a fourth NMOS transistor.

4. The device of claim 3 , wherein the sense amplifier further comprises a second pair of precharge PMOS transistors, wherein a third PMOS transistor of the second pair of precharge PMOS transistors is configured to pull up a voltage at a gate of a fifth PMOS transistor and a gate of the first NMOS transistor, and wherein a fourth PMOS transistor of the second pair of precharge PMOS transistors is configured to pull up a voltage at a gate of a sixth PMOS transistor and a gate of the third NMOS transistor.

5. The device of claim 4 , wherein the first PMOS transistor and the fourth PMOS transistor are coupled in series with the second NMOS transistor via the first NMOS transistor, wherein the second PMOS transistor and the third PMOS transistor are coupled in series with the fourth NMOS transistor via the third NMOS transistor, wherein the second NMOS transistor is coupled in series between the first PMOS transistor and a fifth NMOS transistor, and wherein the fourth NMOS transistor is coupled in series between the second PMOS transistor and the fifth NMOS transistor.

6. The device of claim 4 , wherein a first input of the cross-coupled NAND gates is coupled to a terminal of the fourth PMOS transistor, to a terminal of the first PMOS transistor, and to a second terminal of the first NMOS transistor, wherein a second input of the cross-coupled NAND gates is coupled to a terminal of the third PMOS transistor, to a terminal of the second PMOS transistor, and to a second terminal of the third NMOS transistor, and wherein the cross-coupled NAND gates are configured to generate the first output signal.

7. The device of claim 1 , wherein the first input signal comprises a differential signal, and wherein the cross-coupled NAND gates are configured to generate the first output signal.

8. The device of claim 1 , wherein the sense amplifier includes a first output node coupled to a first input terminal of a first NAND gate of the cross-coupled NAND gates and includes a second output node coupled to a second input of a second NAND gate of the cross-coupled NAND gates.

9. The device of claim 8 , wherein a third input terminal of the first NAND gate is coupled to a first output terminal of a second NAND gate, and wherein a fourth input terminal of the second NAND gate is coupled to a second output terminal of a first NAND gate.

10. The device of claim 1 , wherein the sense amplifier comprises four precharge p-type metal oxide semiconductor (PMOS) transistors, each precharge PMOS transistor having a gate configured to receive to an enable signal.

11. The device of claim 1 , wherein the sense amplifier comprises an internal node coupled to a source/drain of a precharge p-type metal oxide semiconductor (PMOS) transistor and a source/drain of each of a first n-type metal oxide semiconductor (NMOS) transistor and a second NMOS transistor.

12. The device of claim 1 , further comprising:
a coder/decoder;
a digital signal processor coupled to the coder/decoder via the first bus line and the second bus line, wherein the coder/decoder and the digital signal processor are incorporated into a mobile communication device; and
an antenna coupled to the digital signal processor and configured to transmit and receive encoded signals.

13. A method comprising:
receiving a first input signal at a first delay element, wherein the first delay element includes a sense amplifier coupled to a first bus line, and wherein the sense amplifier includes cross-coupled NAND gates; and
generating a first output signal at the first delay element based on the first input signal, wherein the first output signal transitions logic levels after a first delay period responsive to the first input signal transitioning from a logic high level to a logic low level, and wherein the first output signal transitions logic levels after a second delay period responsive to the first input signal transitioning from the logic low level to the logic high level.

14. The method of claim 13 , further comprising:
receiving a second input signal at a second delay element, wherein the second delay element is coupled to a second bus line, and wherein the second delay element receives the second input signal concurrently with the first delay element receiving the first input signal; and
generating a second output signal at the second delay element.

15. The method of claim 14 , wherein, responsive to the first output signal and the second output signal transitioning to opposite logic levels, a difference between the first delay period and the second delay period prevents the first output signal and the second output signal from transitioning to opposite logic levels simultaneously.

16. The method of claim 13 , further comprising:
pulling up a voltage at a terminal of a first n-type metal oxide semiconductor (NMOS) transistor and a terminal of a second NMOS transistor by a first p-type metal oxide semiconductor (PMOS) transistor of a first pair of precharge PMOS transistors of the sense amplifier; and
pulling up a voltage at a terminal of a third NMOS transistor and a terminal of a fourth NMOS transistor by a second PMOS transistor of the first pair of precharge PMOS transistors.

17. The method of claim 16 , further comprising:
pulling up a voltage at a gate of a fifth PMOS transistor and a gate of the first NMOS transistor by a third PMOS transistor of a second pair of precharge PMOS transistors of the sense amplifier; and
pulling up a voltage at a gate of a sixth PMOS transistor and a gate of the third NMOS transistor by a fourth PMOS transistor of the second pair of precharge PMOS transistors.

18. The method of claim 17 , further comprising applying an enable signal to a gate of the first PMOS transistor,

Assignees

• Qualcomm Inc

Inventors

• Mohammad Baker S
• Bassett Paul D
• Saint-Laurent Martin

Classifications

• G06F3/00 Primary

  Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements · CPC title

• G06F13/4077 Primary

  Precharging or discharging · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• H03K3/356069

  using additional transistors in the feedback circuit (H03K3/356104, H03K3/3562 take precedence) · CPC title

• G06F13/4291

  using a clocked protocol · CPC title