Memory controller with multimodal control over memory dies

Patent metadata

Field	Value
Publication number	US-9785572-B1
Application number	US-201615074778-A
Country	US
Kind code	B1
Filing date	Mar 18, 2016
Priority date	Sep 9, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

First claim

What is claimed is:

1. A memory controller integrated circuit to control flash memory comprising flash memory dies, the flash memory dies comprising erase units of memory cells that must be erased together, the memory controller integrated circuit comprising:
at least one host interface to receive memory access requests from a host, each memory access request specifying a logical address in the flash memory;
at least one memory interface to exchange data with the flash memory in fulfilment of the memory access requests according to physical addresses specified by the memory controller integrated circuit; and
circuitry to translate each logical address to a corresponding one of the physical addresses, wherein the circuitry comprises
storage to programmably-receive a setting defining, for a set of the flash memory dies, a selective one of (a) a first mode of operation, pursuant to which successive writes are to be directed to respective erase units in respective ones of the flash memory dies in the set, or (b) a second mode of operation, pursuant to which the successive writes are to be directed to a common erase unit in a single one of the flash memory dies in the set,
circuitry to identify from the logical address a die address and a page address, and
circuitry to store at least one address translation table, the at least one address translation table to output a physical address in response to each logical address.

2. The memory controller integrated circuit of claim 1 , wherein the storage is to programmably-receive a specification of a number of structural elements at a predetermined hierarchical level within the flash memory, the specified number of structural elements free to be other than a power of two, and where circuitry to identify comprises circuitry to apply a modulo operation dependent on the specified number of the structural elements to obtain a first address corresponding to one of the structural elements at the predetermined hierarchical level, and second address corresponding to a remainder of the modulo operation, wherein further, the at least one address translation table is to output the physical address as a function of the remainder.

3. The memory controller integrated circuit of claim 2 , wherein the circuitry to apply is to perform the modulo operation to obtain the first address using pre-configured logic gates, so as to not require individualized assistance of instructional logic to derive each first address from a corresponding one of the logical addresses.

4. The memory controller integrated circuit of claim 2 , wherein the structural elements comprise one of channels, dies, planes and erase units.

5. The memory controller integrated circuit of claim 4 , wherein the number of the structural elements at the predetermined hierarchical level is a first number of first structural elements at a first predetermined hierarchical level, wherein the one of channels, dies, planes and erase units comprises a first one of channels, dies, planes and erase units, and wherein:
the storage is further to programmably receive a specification of a second number of second structural elements at a second predetermined hierarchical level within the nonvolatile memory, the second specified number of second structural elements free to be other than a power of two, and where circuitry to apply the modulo operation is further to apply a second modulo operation to the second address, to obtain a third address corresponding to one of the structural elements at the second predetermined hierarchical level, and fourth address corresponding to a remainder of the second modulo operation, wherein further, the at least one address translation table is to output the physical address as a function of the remainder of the second modulo operation; and
the second specified number corresponds to a second one of channels, dies, planes and erase units.

6. The memory controller integrated circuit of claim 1 , wherein:
the circuitry to identify is to identify the page address as a result of a modulo operation applied to at least part of the logical address.

7. The memory controller integrated circuit of claim 6 , wherein:
the circuitry to identify is also to identify the die address as a result of a modulo operation applied to the at least part of the logical address.

8. The memory controller integrated circuit of claim 1 , wherein the set is a first set, and wherein:
the storage is further to programmably-receive a definition associating the flash memory dies in the first set with a first virtual block device to be controlled by the memory controller integrated circuit;
the storage is further to programmably-receive a definition associating a second set of the flash memory dies with a second programmably-defined virtual block device to be controlled by the memory controller integrated circuit;
each of the memory access requests is to be directed to an exclusive one of the first virtual block device and the second virtual block device;
a number of the flash memory dies in each of the first set and the second set is configurable, with the storage identifying a first configurable number of the flash memory dies with the first set and a second configurable number of the flash memory dies with the second set; and
the second configurable number is free to be different than the first configurable number.

9. The memory controller integrated circuit of claim 8 , wherein:
the setting is a first setting, to be applied to the flash memory dies in the first set;
the storage is also to programmably-receive a second setting, to be applied to the flash memory dies in the second set, the second setting defining a selective one of (a) a first mode of operation, pursuant to which successive writes directed to the second virtual block device are to be directed to respective ones of the flash memory dies in the second set, or (b) a second mode of operation, pursuant to which the successive writes directed to the second virtual block device are to be directed to a single one of the flash memory dies in the second set.

10. The memory controller integrated circuit of claim 8 , wherein the logical addresses are each to be mapped to an exclusive one of the first virtual block device and the second virtual block device by said memory controller integrated circuit, wherein further:
the circuitry to identify is to apply a first modulo operation to logical addresses mapped to the first virtual block device in order to obtain physical page addresses associated with the first virtual block device and is to apply a second modulo operation to logical addresses mapped to the second virtual block device in order to obtain physical page addresses associated with the second virtual block device, in a manner such that the first and second modulo operations generate respective remainders relative to different number spaces.

11. The memory controller integrated circuit of claim 8 , wherein:
each one of the first and second virtual block devices is characterized by associated performance characteristics comprising a time to program a page of memory cells in the flash memory, a time to erase memory cells in the flash memory, and a time to read a page of memory cells in the flash memory;
the memory controller integrated circuit further comprises circuitry to track on an independent basis for each one of the first and second virtual block devices, the need for a maintenance operation, the maintenance operation for each of the first and second virtual block devices comprising at least one of erase memory cells or a data relocation operation for data stored in a page of memory cells; and
the memory controller integrated circuit further compr

Assignees

• Radian Memory Systems Llc
• Radian Memory Systems Inc

Inventors

• Lercari Robert
• Chen Alan
• Jadon Mike
• Robertson Craig
• Kuzmin Andrey V

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title