Memory access method, buffer scheduler and memory module

Patent metadata

Field	Value
Publication number	US-9785551-B2
Application number	US-201514953320-A
Country	US
Kind code	B2
Filing date	Nov 28, 2015
Priority date	May 30, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

First claim

What is claimed is:

1. A memory access method, comprising:
receiving an operation request message for memory access data, wherein the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data, wherein the tag information of the memory access data comprises a tag type, and wherein the tag type instructs a buffer scheduler to perform an operation on at least one of the memory access data and a tag of the memory access data; and
performing, according to at least one of the tag information of the memory access data, the memory address of the memory access data, and the operation information of the memory access data, the operation on the at least one of the tag of the memory access data and the memory access data that are stored in a memory module;
wherein the performing the operation on the at least one of the tag of the memory access data and the memory access data comprises determining, according to the tag type, whether to perform an operation on the tag of the memory access data, and performing the operation on at least one of the tag of the memory access data.

2. The method according to claim 1 , wherein the performing, according to at least one of the tag information of the memory access data, the memory address of the memory access data, and the operation information of the memory access data, an operation on at least one of the tag of the memory access data and the memory access data that are stored in a memory module comprises:
using, in response to the determining to perform the operation on the tag of the memory access data, the memory address of the memory access data as an index and querying a pre-stored memory access tag location mapping table to determine a memory address of the tag of the memory access data, and performing, according to at least one of the tag information of the memory access data, the memory address of the tag of the memory access data, the memory address of the memory access data, and the operation information of the memory access data, the operation on at least one of the tag of the memory access data or both the tag of the memory access data and the memory access data; and
performing, in response to determining to not perform the operation on the tag of the memory access data, and according to at least the memory address of the memory access data and the operation information of the memory access data, the operation on the memory access data that is stored in the memory module.

3. The method according to claim 2 , wherein the tag information of the memory access data includes the tag type and tag content; and
wherein the using the memory address of the memory access data as the index and the querying the pre-stored memory access tag location mapping table to determine the memory address of the tag of the memory access data comprises:
determining whether a mapping relationship between the memory address of the memory access data and the memory address of the tag of the memory access data is stored in the pre-stored memory access tag location mapping table;
acquiring, in response to determine that the mapping relationship between the memory address of the memory access data and the memory address of the tag of the memory access data is stored in the pre-stored memory access tag location mapping table, the memory address of the tag of the memory access data from the pre-stored memory access tag location mapping table according to the memory address of the memory access data; and
determining, in response to determine that the mapping relationship between the memory address of the memory access data and the memory address of the tag of the memory access data is not stored in the pre-stored memory access tag location mapping table, the tag content in the tag information of the memory access data as the tag of the memory access data, selecting, from the memory module, space that is greater than or equal to a tag granularity of the tag as the memory address of the tag of the memory access data, writing the tag into the memory address, and storing the mapping relationship between the memory address of the memory access data and the memory address of the tag of the memory access data into the pre-stored memory access tag location mapping table.

4. A memory access method, comprising:
receiving at least one of a first message and a second message sent by a buffer scheduler in response to a central processing unit sending an operation request message for memory access data to a buffer scheduler, wherein the first message carries a memory address of a tag of the memory access data and operation information about an operation on the tag of the memory access data, and wherein the second message carries a memory address of the memory access data and operation information about an operation on the memory access data; and
performing the operation on at least one of the tag of the memory access data and the memory access data according to at least one of the first message and the second message;
wherein performing the operation on at least one of the tag of the memory access data and the memory access data comprises:
acquiring the tag of the memory access data according to the memory address of the tag of the memory access data carried in the first message; and
performing the operation on the acquired tag of the memory access data according to the operation information about the operation on the tag of the memory access data carried in the first message.

5. The method according to claim 4 , wherein the memory address of the tag of the memory access data and the memory address of the memory access data are different physical addresses in a memory module.

6. The method according to claim 4 ,
wherein the performing the operation on the memory access data according to the second message comprises:
acquiring the memory access data according to the memory address of the memory access data carried in the second message; and
performing the operation on the acquired memory access data according to the operation information about the operation on the memory access data carried in the second message.

7. A buffer scheduler, comprising
a receiver configured to receive an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data, wherein the tag information of the memory access data includes a tag type, and wherein the tag type instructs to perform an operation on at least one of the memory access data and a tag of the memory access data;
a processor connected to the receiver;
a non-transitory computer readable medium connected to the processor and having stored thereon instructions that, when executed by the processor, cause the buffer scheduler to:
perform, according to at least one of the tag information of the memory access data, the memory address of the memory access data, and the operation information of the memory access data, the operation on at least one of the tag of the memory access data and the memory access data that are stored in a memory module, wherein the instructions that cause the buffer schedule to perform the operation on the at least one of the tag of the memory access data and the memory access data include instructions that cause the buffer scheduler to determine, according to the tag type, whether to perform an operation on the tag of the memory access data, and perform the operation on at least one of the tag of the memory access data.

8. The buffer scheduler according to claim 7 , wherein the instructions causing the buffer sc

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Yongbing
• Chen Mingyu
• Chen Licheng
• Cui Zehan

Classifications

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F12/0284 Primary

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F2212/2532

  comprising a plurality of modules · CPC title