Method for operating a control unit and a control unit having a model calculation unit

Patent metadata

Field	Value
Publication number	US-9785410-B2
Application number	US-201414321306-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 2, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A method for operating a control unit, the control unit including a software-controlled main processing unit, a strictly hardware-based model calculation unit for calculating an algorithm, for carrying out a Bayesian regression method, based on configuration data, and a memory unit, a model memory area being defined in the memory unit to which a configuration register block for providing the configuration data in the model calculation unit is assigned, a calculation start-configuration register being assigned the highest address in the configuration register block into which configuration data are written, the writing into of which starts the calculation in the model calculation unit, the configuration data being written in a memory area of the memory unit from the model memory area into the configuration register block with an incremental copying process, the addresses being copied in the incremental copying process in ascending order.

First claim

What is claimed is:

1. A method for operating a control unit for calculating an algorithm, the method comprising:
defining a model memory area in a memory unit to which a configuration register block for providing configuration data in a strictly hardware-based model calculation unit is assigned, wherein the control unit includes a software-controlled main processing unit, the memory unit, and the strictly hardware-based model calculation unit for calculating an algorithm based on configuration data; and
assigning a calculation start-configuration register a highest address in the configuration register block into which configuration data is written, the writing of which starts the calculation in the model calculation unit, the configuration data being written in a memory area of the memory unit from the model memory area into the configuration register block with an incremental copying process, the addresses being copied in the incremental copying process in sequential order.

2. The method of claim 1 , wherein the incremental copying process is carried out with the aid of a block copying function of a DMA unit.

3. The method of claim 2 , wherein the incremental copying process exhibits a granularity, an unused memory area being connected to the memory address assigned to the calculation start-configuration register, to fit the granularity of the DMA unit.

4. The method of claim 2 , wherein the DMA unit is instructed by the main processing unit to carry out multiple successive block copying functions having a same destination base address.

5. The method of claim 4 , wherein in accordance with the instruction of the DMA unit to carry out multiple successive block copying functions, multiple calculations are carried out in the model calculation unit, and wherein a second DMA unit copies the calculation result after each calculation started by the multiple block copying process and instructing the first DMA unit to carry out the next block copying process to be carried out.

6. The method of claim 1 , wherein the algorithm includes carrying out a Bayesian regression method.

7. The method of claim 1 , wherein the sequential order is an ascending order.

8. A control unit for operating a physical unit, comprising:
a software-controlled main processing unit;
a strictly hardware-based model calculation unit for calculating an algorithm, for carrying out a Bayesian regression method, based on configuration data; and
a memory unit for storing the configuration data, a model memory area being defined in the memory unit to which a configuration register block is assigned for providing the configuration data in the model calculation unit, a calculation start-configuration register being assigned a highest address in the configuration register block;
wherein the model calculation unit is configured to start a calculation of the algorithm when the calculation start-configuration register is written into.

9. The control unit of claim 8 , further comprising:
a first DMA unit to carry out the writing into the configuration register block with a block copying process.

10. The control unit of claim 9 , wherein the main processing unit starts the function of the first DMA unit.

11. The control unit of claim 9 , wherein the main processing unit is configured to prompt the first DMA unit to carry out a multiple block copying process, after which multiple successive calculations are carried out in the model calculation unit.

12. The control unit of claim 11 , further comprising:
a second DMA unit to copy the calculation result after each calculation started by the multiple block copying process and to instruct the first DMA unit to carry out the next block copying process.

13. A non-transitory computer readable medium having a computer program, which is executable by a processor, comprising:
a program code arrangement having program code for operating a control unit for calculating an algorithm, by performing the following:
defining a model memory area in a memory unit to which a configuration register block for providing configuration data in a strictly hardware-based model calculation unit is assigned, wherein the control unit includes a software-controlled main processing unit, the memory unit, and the strictly hardware-based model calculation unit for calculating an algorithm based on configuration data; and
assigning a calculation start-configuration register a highest address in the configuration register block into which configuration data is written, the writing of which starts the calculation in the model calculation unit, the configuration data being written in a memory area of the memory unit from the model memory area into the configuration register block with an incremental copying process, the addresses being copied in the incremental copying process in sequential order.

14. The computer readable medium of claim 13 , wherein the algorithm includes carrying out a Bayesian regression method.

15. The computer readable medium of claim 13 , wherein the sequential order is an ascending order.

Assignees

• Bosch Gmbh Robert

Inventors

• Markert Heiner
• Fischer Wolfgang
• Bannow Nico
• Guntoro Andre
• Hanselmann Michael

Classifications

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G05B13/04 Primary

  involving the use of models or simulators · CPC title

• G06F7/60 Primary

  Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations {, e.g. using difunction pulse trains, STEELE computers, phase computers (conversion of digital data to or from non-denominational form H03M5/00, H03M7/00)} · CPC title

• G05B19/0426 Primary

  Programming the control sequence · CPC title