Operating method of nonvolatile memory device and nonvolatile memory system

Patent metadata

Field	Value
Publication number	US-9785379-B2
Application number	US-201514616153-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Feb 6, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation.

First claim

What is claimed is:

1. An operating method of a nonvolatile memory device which includes a buffer region including a first plurality of memory cells and a main region including a second plurality of memory cells, the method comprising:
receiving a plurality of sub-page data and a write command from an external device;
performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region;
performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and
performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation,
wherein each of the first plurality of memory cells in the buffer region stores N-bit data, each of the second plurality of memory cells in the main region stores M-bit data, each of the plurality of sub-page data indicate data stored in a single page of the nonvolatile memory device,
wherein N is a positive integer and M is a positive integer which is greater than N, and
wherein the pre-main programming and the re-main programming are performed based on bit ordering which indicates a corresponding relationship between data stored in a memory cell in the main region and a plurality of program states.

2. The operating method as set forth in claim 1 , wherein the performing the re-main program operation comprises:
reading the received sub-page data, subjected to the buffered program operation, from the buffer region; and
performing the re-main program operation such that the read sub-page data is stored in the second plurality of memory cells subjected to pre-main program operation.

3. The operating method as set forth in claim 1 , wherein the re-main program operation is an operation to reprogram the other sub-page data into the second plurality of memory cells subjected to the pre-main program operation.

4. The operating method as set forth in claim 1 , wherein the write command is an on-chip buffered program (OBP) command.

5. The operating method as set forth in claim 1 , further comprising:
receiving an address from the external device,
wherein the pre-main program operation is performed such that the at least one of the plurality of sub-page data is stored in a third plurality of memory cells which correspond to the address among the second plurality of memory cells in the main region.

6. The operating method as set forth in claim 1 , further comprising:
receiving a buffer address from the external device,
wherein the buffered program operation is performed such that the other sub-page data is stored in a third plurality of memory cells which correspond to the buffer address among the first plurality of memory cells in the buffer region.

7. The operation method as set forth in claim 1 , wherein the nonvolatile memory device includes a memory cell array including the buffer region and the main region, and the memory cell array includes a plurality of cell strings,
wherein each of the plurality of cell strings includes a third plurality of memory cells which is stacked to be perpendicular to a substrate, a ground selection transistor provided between the third plurality of memory cells and the substrate, and a string selection transistor provided between the third plurality of memory cells and a bitline.

8. The operating method as set forth in claim 1 , wherein the at least one sub-page data subjected to the pre-main programming is predetermined sub-page data which satisfies a reference condition,
wherein the reference condition indicates a condition in which an upper limit of a threshold voltage distribution of a program state of the second plurality of memory cells subjected to the pre-main programming is made maximum.

9. An operating method of a nonvolatile memory device which includes a plurality of memory cells, the method comprising:
performing a first program operation such that N-bit data is stored in at least one of the plurality of memory cells;
performing a second program operation in the plurality of memory cells which have been programmed with a first program operation, such that M-bit data is stored;
wherein the second program operation is performed in the plurality of memory cells subjected to the first program operation,
wherein N is a positive integer and M is a positive integer which is greater than N,
wherein the nonvolatile memory device includes a first region including the at least one of the plurality of memory cells and a second region including other memory cells,
wherein the operating method further comprises receiving a plurality of sub-page data and a write command from an external device; and performing a third program operation such that at least one of the plurality of sub-page data is stored in the other memory cells included in the second region,
wherein the performing the first program operation comprises performing the first program operation such that other received sub-page data is stored in the at least one of the plurality of memory cells included in the first region,
wherein the performing the second program operation comprises performing the second program operation such that the received sub-page data subjected to the third program operation at the second region is stored in the at least one of the plurality of memory cells subjected to the first program operation,
wherein the at least one of a plurality of memory cells programmed with the first program operation stores N-bit data, at least one of a plurality of memory cells programmed with the second program operation stores M-bit data, and at least one of a plurality of memory cells programmed with the third program operation stores L-bit data, and
wherein N is a positive integer, L is a positive integer which is lower than M.

10. The operating method as set forth in claim 9 , wherein N is two and M is four.

11. The operating method as set forth in claim 9 , wherein M is greater than four.

12. A nonvolatile memory system comprising:
a nonvolatile memory device including a first region and a second region; and
a memory controller configured to receive data from an external device, to store a part of the received data in the first region, and to store another part of the received data in the second region,
wherein the memory controller is configured to store the part of the received data, which is stored in the first region, in a plurality of memory cells which store another of the received data among a plurality of memory cells in the second region,
wherein the nonvolatile memory device is configured to read the part of the received data stored in the first region, and to perform a third program operation such that the read part of the received data is stored in the plurality of the memory cells storing another part of the received data among the plurality of memory cells in the second region under a control of the memory controller,
wherein the memory controller is configured to store L-bits data in the first region,
the memory controller is configured to store N-bits data in the second region and the memory controller is configured to store M-bits data in the second region, and
wherein L is a positive integer and N is a positive integer, and M is an integer which is greater than N.

13. The nonvolatile memory system as set forth in claim 12 ,
wherein each of the first region and the second region comprises a plurality of memory cells,
wherein e

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Eun Chu
• Kim Jongha
• Kong Junjin
• Son Hong Rak

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title