Low power timing, configuring, and scheduling

Patent metadata

Field	Value
Publication number	US-9785219-B2
Application number	US-201414524844-A
Country	US
Kind code	B2
Filing date	Oct 27, 2014
Priority date	May 7, 2012
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

First claim

What is disclosed is:

1. A device for triggering performance of a task on a time schedule comprising:
a component for performing the task and having an active state and an inactive state of operation;
a counter receiving a clock signal at an input, and producing a count signal at an output;
a first register for storing a first comparison value;
a second register for storing a second comparison value larger than the first comparison value; and
a comparison block for triggering the performance of the task by the component on the time schedule based on the count signal and the first and second comparison values,
wherein based on a comparison of the count signal and the first comparison value, the comparison block triggers the component to perform the task when the component operates in the active state, and
wherein based on a comparison of the count signal and the second comparison value, the comparison block changes the state of operation of the component to the active state to trigger the component to perform the task.

2. The device as in claim 1 , wherein the comparison block changes the state of operation of the component only if the comparison block previously or concurrently triggered the component to perform the task.

3. The device as in claim 1 , further comprising:
an adder for receiving the count signal as one addend and the first comparison value as another addend, and for producing an adder output signal value;
a latch for holding the adder output signal value;
wherein the comparison block receives the count signal, an output signal of the latch, and the second comparison value, and triggers the performance of the task by the component on the time schedule based on the count signal, the output signal of the latch, and the second comparison value; and
wherein the latch holds the adder output signal value received at the time the first comparison value is loaded in the first register.

4. The device as in claim 1 , further comprising:
an adder for receiving the count signal as one addend and the second comparison value as another addend, and for producing an adder output signal value;
a latch for holding the adder output signal value;
wherein the comparison block receives the count signal, the first comparison value, and an output signal of the latch, and triggers the performance of the task by the component on the time schedule based on the count signal, the first comparison value, and the output signal of the latch; and
wherein the latch holds the adder output signal value received at the time the second comparison value is loaded in the second register.

5. The device as in claim 1 , further comprising:
an adder for receiving the first comparison value as one addend and the second comparison value as another addend, and for producing an adder output signal value;
a latch for holding the adder output signal value;
wherein the comparison block receives the count signal, the first comparison value, and an output signal of the latch, and triggers the performance of the task by the component on the time schedule based on the count signal, the first comparison value, and the output signal of the latch; and
wherein the latch holds the adder output signal value received at the time the second comparison value is loaded in the second register.

6. The device as in claim 1 , further comprising:
a first adder for receiving the count signal as one addend and the first comparison value as another addend, and for producing a first adder output signal value;
a second adder for receiving the count signal as one addend and the second comparison value as another addend, and for producing a second adder output signal value;
a first latch for holding the first adder output signal value;
a second latch for holding the second adder output signal value;
wherein the comparison block receives the count signal and output signals of each of the first and second latches, and triggers the performance of the task by the component on the time schedule based on the count signal and the output signals of each of the first and second latches; and
wherein the first and second latches respectively hold the first and second adder output signal values received at the time that an output control signal is asserted.

7. The device as in claim 6 , wherein the output control signal is asserted when the comparison block, based on a comparison of the count signal and the output signal of the first latch, triggers the component to perform the task when the component operates in the active state.

8. The device as in claim 6 , wherein the output control signal is asserted when the comparison block, based on a comparison of the count signal and the output signal of the second latch, changes the state of operation of the component to the active state.

9. The device as in claim 1 , wherein the comparison block comprises:
a multiplexer having first and second inputs respectively coupled to the first and second registers;
a comparator having one input coupled to an output of the multiplexer and an other input coupled to the counter;
a demultiplexer having an output selectively controlled to produce a signal for triggering the component to perform the task or to produce a signal for changing the state of operation of the component;
wherein the multiplexer selects whether the first or second comparison value is transmitted to the comparator, and wherein the demultiplexer selects whether to produce the signal for triggering or the signal for changing.

10. The device as in claim 1 , wherein the comparison block comprises:
a first comparator with one input coupled to the first register and the other input coupled to the counter;
a second comparator with one input coupled to the second register and the other input coupled to the counter;
wherein the first comparator generates a signal for triggering the component to perform the task; and
wherein the second comparator generates a signal for changing the state of operation of the component.

Assignees

• Dust Networks Inc
• Linear Tech Corp

Inventors

• Warneke Brett

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04W52/0203 Primary

  in the radio access network or backbone network of wireless communication networks · CPC title