Active device array substrate and display panel

Patent metadata

Field	Value
Publication number	US-9785032-B2
Application number	US-201514927498-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Nov 12, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A display panel includes a display panel body, a first protective film, a second protective film, and a sealant. The display panel body has a first surface, a second surface opposite to the first surface, and a first through hole that passes through the display panel body and connects the first surface and the second surface. The first protective film is arranged on the first surface and has a second through hole connected to the first through hole. The second protective film is arranged on the second surface. The sealant fills the first through hole, so that a sidewall of the display panel body which is exposed by the first through hole is sealed, and a material of the sealant is a curable material.

First claim

What is claimed is:

1. An active device array substrate, comprising:
a substrate having a reference axis, an active area, a periphery area located around the active area and a through hole passing through the substrate and located in the active area, wherein the reference axis divides the active area into a first region and the second region;
a plurality of first signal lines disposed in the active area of the substrate, wherein a portion of the first signal lines bypass the through hole;
a plurality of second signal lines disposed on the substrate and interlacing with the first signal lines, wherein a portion of the second signal lines bypass the through hole;
a plurality of pixel units disposed within the active area and electrically connected to the corresponding first signal lines and the corresponding second signal lines;
a plurality of selection lines disposed on the substrate and extending from the active area to the periphery area along with the second signal lines, wherein a portion of the selection lines bypass the through hole;
an insulating layer disposed among the first signal lines, the second signal lines, and the selection lines and having a plurality of contact holes, the contact holes disposed corresponding to the first signal lines, and a portion of the selection lines electrically connected to the first signal lines respectively via the contact holes, wherein the contact holes are divided into a plurality of first contact holes located within the first region and a plurality of second contact holes located within the second region;
a sealant filling the through hole, so as to seal a sidewall of the substrate exposed by the through hole, a material of the sealant being a curable material; and
a driving unit disposed on the substrate and located in the periphery area, wherein the second signal lines and a portion of the selection lines are electrically connected to the driving unit, wherein a position of a first connection line formed by orthogonal projection positions of the first contact holes formed on the substrate is disposed in a direction farthest from the driving unit and closest to the reference axis toward a direction close to the driving unit and distant from the reference axis, a position of a second connection line formed by orthogonal projection positions of the second contact holes formed on the substrate is disposed in a direction closest to the driving unit and the reference axis toward a direction distant from the driving unit and the reference axis, and the selection line corresponding to the first contact hole farthest from the driving unit and closest to the reference axis, and the selection line corresponding to the second contact hole closest to the driving unit and the reference axis, respectively, are configured to receive a start signal and a terminal signal provided by the driving unit.

2. The active device array substrate as recited in claim 1 , wherein the driving unit comprises at least one first driving unit and a plurality of second driving units, and the first driving unit is located between the second driving units.

3. The active device array substrate as recited in claim 2 , wherein one of the first driving unit and each of the second driving units is a gate driving unit, and the other one of the first driving unit and each of the second driving units is a source driving unit.

4. The active device array substrate as recited in claim 2 , wherein the at least one first driving unit is a plurality of first driving units, and the first driving units and the second driving units are disposed alternately.

5. The active device array substrate as recited in claim 2 , wherein the second signal lines are electrically connected to the first driving unit, and the selection lines are electrically connected to the second driving units.

6. The active device array substrate as recited in claim 1 , wherein the selection lines and the second signal lines are arranged in parallel in the active area, and the selection lines and the second signal lines connected to the driving unit in the periphery area are non-interlaced with one another.

7. The active device array substrate as recited in claim 1 , wherein each of the selection lines is located between the two adjacent second signal lines, and a number of the pixel units in a longest column is equivalent to a number of the pixel units in a longest row.

8. The active device array substrate as recited in claim 7 , wherein the position of the first connection line formed by the orthogonal projection positions of the first contact holes formed on the substrate and the position of the second connection line formed by the orthogonal projection positions of the second contact holes formed on the substrate are two parallel lines.

9. The active device array substrate as recited in claim 1 , wherein the selection lines comprise a plurality of first selection lines and a plurality of second selection lines, each of the first selection lines and each of the second selection lines are located between the two adjacent second signal lines, and a number of the pixel units in a longest column is greater than a number of the pixel units in a longest row.

10. A display panel comprising:
a display panel body having a first surface, a second surface opposite to the first surface, and a first through hole passing through the display panel body and connecting the first surface and the second surface, wherein the display panel body comprises the active device array substrate as claimed in claim 1 ;
a first protective film arranged on the first surface, the first protective film having a second through hole connected to the first through hole;
a second protective film arranged on the second surface; and
a sealant filling the first through hole, so as to seal a sidewall of the display panel body exposed by the first through hole, a material of the sealant being a curable material.

11. The display panel as recited in claim 10 , wherein a width of the second through hole is smaller than a width of the first through hole.

12. The display panel as recited in claim 10 , wherein a width of the second through hole is equal to a width of the first through hole.

13. The display panel as recited in claim 10 , wherein the curable material comprises epoxy resin, ultraviolet curing adhesive, or thermal-setting adhesive.

14. The display panel as recited in claim 10 , wherein the second protective film has a third through hole, the sealant has a fourth through hole, and the fourth through hole is connected between the second through hole and the third through hole.

15. The display panel as recited in claim 14 , wherein a sidewall of the first protective film exposed by the second through hole, a sidewall of the sealant exposed by the fourth through hole, and a sidewall of the second protective film exposed by the third through hole constitute a continuous surface.

16. The display panel as recited in claim 15 , wherein a width of the second through hole, a width of the third through hole, and a width of the fourth through hole are identical.

17. The display panel as recited in claim 15 , wherein a width of the second through hole, a width of the third through hole, and a width of the fourth through hole gradually decrease in a direction perpendicular to the display panel, the width of the fourth through hole and the width of the second through hole are identical at an intersection of the sealant and the first protective film, and the width of the fourth through hole and the width of the third through hole are identical at an intersection

Assignees

• E Ink Holdings Inc

Inventors

• Chiang Ming-Sheng
• Wu Chi-Ming

Classifications

• H10W90/00

  Package configurations · CPC title

• G09G3/344

  based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H01L2924/00

  Electricity · mapped topic

• G02B1/14

  Protective coatings, e.g. hard coatings · CPC title