Method for making a suspended membrane structure with buried electrode

Patent metadata

Field	Value
Publication number	US-9783407-B2
Application number	US-201213546411-A
Country	US
Kind code	B2
Filing date	Jul 11, 2012
Priority date	Jul 12, 2011
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A microsystem and/or nanosystem type device is disclosed, comprising:
a first substrate, or intermediate substrate, comprising a mobile part, a second substrate or support substrate, at least one lower electrode, and one dielectric layer ( 101 ) located between the first and second substrates, the dielectric layer being arranged between the lower electrode and the first substrate; the first substrate comprising through vias filled with conducting material in contact with said lower electrode.

First claim

The invention claimed is:

1. At least one of a microsystem or a nanosystem device comprising:
a first substrate, being an intermediate substrate, comprising a mobile part,
a second substrate being a support substrate,
at least one first electrode, being a lower electrode, formed of at least one conducting material, defined in a lower electrode layer, and one dielectric layer located between the first and second substrates,
the dielectric layer being arranged in part or in whole between the lower electrode and the first substrate,
a cavity disposed under the mobile part of the system,
said lower electrode disposed under said cavity and having a top part facing at least part of the mobile part spaced apart from the mobile part,
the first substrate comprising at least one through via filled with said at least one conducting material,
said at least one through via and said lower electrode, both formed during a continuous process filling the at least one through via and forming the lower electrode, thereby both comprising identically the same said at least one conducting material throughout without interruption, and
a bottom surface of the mobile part of the first substrate is exposed to the cavity.

2. The device according to claim 1 , further comprising a second electrode, being an upper electrode, located on the first substrate, and in electrical contact with the at least one through via passing through the first substrate.

3. The device according to claim 2 , the upper electrode being located on the intermediate substrate using conductors, or being supported by a third substrate.

4. The device according to claim 1 , also comprising electrical contact zones between the lower electrode and the first substrate.

5. The device according to claim 1 , the first substrate being made of a semiconducting material, for example silicon, or SiGe or SiC or SiGeC or GaAs or Ge or a semiconducting material in Group III-V, preferably doped, or a “silicon on insulator” (SOI) type substrate.

6. The device according to claim 1 , the first substrate comprising several layers stacked on a substrate.

7. The device according to claim 1 , further comprising a dielectric layer between the second substrate and the lower electrode layer.

8. The device according to claim 7 , etched zones being defined in the lower electrode layer and in the dielectric layer located between the second substrate and the lower electrode layer.

9. The device according to claim 7 , etched zones being defined in the lower electrode layer, said etched zones being filled with the material of said dielectric layer.

10. The device according to claim 1 , wherein the cavity is at least as wide as the mobile part.

11. The device according to claim 1 , wherein the cavity is wider than a width of the mobile part.

12. The device according to claim 1 , wherein the first substrate comprising said at least one through via is filled with said at least one conducting material.

13. The device according to claim 1 , wherein an extension member contacts specific locations of the first substrate to limit parasite capacitance.

14. The device according to claim 1 , wherein an extension member of the lower electrode contacts specific locations of the first substrate.

15. The device according to claim 1 , wherein an extension member contacts specific locations of the first substrate.

16. The device according to claim 15 , wherein the extension member limits parasite capacitance.

Assignees

• Giroud Sophie
• Berthelot Audrey
• Larrey Vincent
• Polizzi Jean-Philippe
• Vaudaine Marie-Hélène
• Commissariat L Energie Atomique Et Aux Energies Alternatives

Inventors

• Giroud Sophie
• Berthelot Audrey
• Larrey Vincent
• Polizzi Jean-Philippe
• Vaudaine Marie-Hélène

Classifications

• B81B2207/07

  Interconnects · CPC title

• B81B3/00 Primary

  Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes (B81B5/00 takes precedence) · CPC title

• B81C1/00166

  Electrodes · CPC title

• B81B2203/04

  Electrodes · CPC title

• B81C1/00015

  for manufacturing microsystems · CPC title