Multinode hubs for trusted computing

Patent metadata

Field	Value
Publication number	US-9781117-B2
Application number	US-201615204799-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Mar 25, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.

First claim

What is claimed is:

1. A multinode hub, comprising:
a plurality of memory regions, wherein each respective memory region is associated with a respective associated coherent computing node of a plurality of coherent computing nodes and to receive trust operation data only from its respective associated coherent computing node, and wherein each of the respective coherent computing nodes sends trust operation data only to its respective associated memory region out of the plurality of memory regions; and
a trusted platform module (TPM) component to process trust operation data in one of the memory regions indicated by a trap notification from a trapping module, wherein a trap notification indicates which of the plurality of memory regions has been accessed.

2. The multinode hub of claim 1 , wherein the TPM component is to verify an integrity of a basic input/output system (BIOS) of the coherent computing node associated with the memory region indicated by the trap notification, as part of processing of the trust operation data in the memory region indicated by the trap notification.

3. The multinode hub of claim 1 , wherein the TPM component is to verify a launch of a hypervisor by the coherent computing node associated with the memory region indicated by the trap notification, as part of processing the trust operation data in the memory region indicated by the trap notification.

4. The multinode hub of claim 1 , further comprising:
the trapping module, coupled with the plurality of memory regions and the TPM component, to generate the trap notification in response to an access to the indicated memory region by the associated coherent computing node.

5. The multinode hub of claim 1 , further comprising non re-writeable memory, wherein firmware associated with the multinode hub is disposed in the non re-writeable memory.

6. The multinode hub of claim 1 , wherein the multinode hub is included in an integrated circuit package along with the plurality of coherent computing nodes.

7. The multinode hub of claim 1 , further comprising one or more serial or parallel buses to couple the plurality of coherent computing nodes with the associated plurality of memory regions to enable the plurality of coherent computing nodes to communicate with the associated plurality of memory regions.

8. The multinode hub of claim 1 , wherein the multinode hub is included in an integrated circuit package separate from a package including at least one of the plurality of coherent computing nodes.

9. The multinode hub of claim 1 , wherein the plurality of memory regions is to receive trust operation data from an operating system of the associated coherent computing node.

10. The multinode hub of claim 1 , wherein base addresses of the plurality of memory regions are included in Advanced Configuration and Power Interface (ACPI) tables of the associated coherent computing nodes.

11. The multinode hub of claim 1 , wherein the plurality of memory regions is to receive trust operation data via a Direct Memory Access (DMA) transfer from the associated coherent computing node.

12. The multinode hub of claim 1 , further comprising a Unified Extensible Firmware Interface (UEFI) Platform Initialization (PI) System Management Mode (SMM) driver having firmware associated with the multinode hub.

13. The multinode hub of claim 1 , wherein the TPM component comprises a memory, and wherein the TPM component is to process trust operation data from memory regions associated with different coherent computing nodes in the memory.

14. A computing system having a multinode hub, comprising:
a plurality of coherent computing nodes; and
the multinode hub, wherein the multinode hub comprises:
a plurality of memory regions, wherein each respective memory region is associated with a respective associated coherent computing node of the plurality of coherent computing nodes and to receive trust operation data only from its respective associated coherent computing node, and wherein each of the respective coherent computing nodes sends trust operation data only to its respective associated memory region out of the plurality of memory regions; and
a trusted platform module (TPM) component to process trust operation data in one of the memory regions indicated by a trap notification from a trapping module, wherein a trap notification indicates which of the plurality of memory regions has been accessed.

15. The computing system of claim 14 , wherein the multinode hub further comprises the trapping module, coupled with the plurality of memory regions, to generate the trap notification in response to an access to the indicated one of the memory regions by the respective associated coherent computing node.

16. The computing system of claim 14 , wherein the multinode hub is included in an integrated circuit package along with the plurality of coherent computing nodes.

17. The computing system of claim 14 , further comprising one or more serial or parallel buses to couple the plurality of coherent computing nodes with the associated plurality of memory regions to enable the plurality of coherent computing nodes to communicate with the associated plurality of memory regions.

18. The computing system of claim 14 , wherein the multinode hub is included in an integrated circuit package separate from a package including at least one of the plurality of coherent computing nodes.

19. The computing system of claim 14 , wherein the TPM component comprises a memory, and wherein the TPM component is to process trust operation data from memory regions associated with different coherent computing nodes in the memory.

Assignees

• Intel Corp

Inventors

• Swanson Robert C
• Nemiroff Daniel
• Zimmer Vincent J
• Bulusu Mallik
• Lindsley John R
• Cone Robert W
• Trivedi Malay
• Kwidzinski Piotr

Classifications

• H04L63/10 Primary

  for controlling access to devices or network resources · CPC title

• G06F21/554 Primary

  involving event detection and direct action · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F21/572

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

• G06F21/57

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title