Analog equalizer

Patent metadata

Field	Value
Publication number	US-9780979-B2
Application number	US-201715412576-A
Country	US
Kind code	B2
Filing date	Jan 23, 2017
Priority date	Feb 3, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

First claim

What is claimed is:

1. An analog equalizer, for equalizing a signal to be equalized, comprising:
an adjusting circuit, generating an adjustment signal and a selection signal;
a cascaded multi-stage equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, and a tunable current source in cascaded multi-stage equalization circuit according to the adjustment signal to perform an equalization process on the signal to be equalized; and
an analog multiplexer, coupled to the cascaded multi-stage equalization circuit and the adjusting circuit, receiving the selection signal, and selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit;
wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

2. The analog equalizer according to claim 1 , wherein the adjusting circuit comprises:
a clock data recovery circuit, generating a clock signal, recovering the equalized signal into a pulse string according to the clock signal
a comparing circuit, coupled to the clock data recovery circuit, comparing the pulse string with a predetermined burst to obtain a comparison result; and
an adjustment/selection signal output circuit, coupled to the comparing circuit, outputting the adjustment signal and the selection signal according to the comparison result.

3. The analog equalizer according to claim 2 , wherein the clock data recovery circuit re-samples the equalized signal according to the clock signal to obtain the pulse string.

4. The analog equalizer according to claim 2 , wherein the comparing circuit compares a characteristic burst in the pulse string with the predetermined burst to obtain the comparison result.

5. The analog equalizer according to claim 3 , wherein when the clock data recovery circuit operates in a first mode, the clock data recovery circuit generates the clock signal according to a signal transmitted in an interface clock channel; when the clock data recovery circuit operates in a second mode, the clock data recovery circuit generates the clock signal according to frequency information in the equalized signal.

6. The analog equalizer according to claim 4 , wherein the comparing circuit compares the characteristic burst with the predetermined burst, and the predetermined burst is a signal burst without attenuation or deformation in a predetermined state.

7. The analog equalizer according to claim 6 , wherein the adjustment/selection signal output circuit repeats outputting the adjustment signal and the selection signal for the equalization process until the equalized signal reaches the target equalization value.

8. The analog equalizer according to claim 1 , wherein the multi-stage equalization circuit comprises an amplification module; the amplification module comprises a first MOS transistor, a second MOS transistor, a first tunable resistor, a second tunable resistor, a third tunable resistor, a first tunable capacitor, a second tunable capacitor, a third tunable capacitor, a first tunable current source and a second tunable current source; the first MOS transistor and the second MOS transistor have respective first input ends receive a differential input signal, and respectively second input ends output a differential output signal; the first MOS transistor further has the second input end connected to one end of the first tunable resistor and one end of the first tunable capacitor; the second MOS transistor further has the second input end connected to one end of the second tunable resistor and one end of the second tunable capacitor; the first tunable resistor has one other end connected to one other end of the second tunable resistor; one other end of the first tunable capacitor and one other end of the second tunable capacitor are connected to ground; the first MOS transistor has a third end connected to one end of the third tunable resistor, one end of the third tunable capacitor and a first end of the first tunable current source; the second MOS transistor has a third end connected to one other end of the third tunable resistor, one other end of the third tunable capacitor and a first end of the second tunable current source; and the first tunable current source has a second end connected to a second end of the second tunable current source.

9. The analog equalizer according to claim 8 , wherein the multi-stage equalization circuit further comprises a latch module; the latch module comprises a third MOS transistor, a fourth MOS transistor, a fourth tunable capacitor, a third tunable current source and a fourth tunable current source; the third MOS transistor has a second end connected to the second input end of the first MOS transistor and a first end of the fourth MOS transistor; the fourth MOS transistor has a second end connected to the second input end of the second MOS transistor and a first end of the third MOS transistor; the third MOS transistor has a third end connected to one end of the fourth tunable capacitor and a first end of the third tunable current source; the fourth OS transistor has a third end connected to one other end of the fourth tunable capacitor and a first end of the fourth tunable current source; and the third tunable current source has a second end connected to a second end of the fourth tunable current source.

10. The analog equalizer according to claim 8 , wherein when the first MOS transistor is an NMOS transistor, the first end, the second end and the third end of the first MOS transistor are a gate, a drain and a source of the NMOS transistor, respectively, the first end and the second end of the first tunable current source are an input end and an output end, respectively, and the output end of the first tunable current source is connected to ground.

11. The analog equalizer according to claim 8 , wherein when the first MOS transistor is a PMOS transistor, the first end, the second end and the third end of the first MOS transistor are a gate, a drain and a source of the PMOS transistor, respectively, the first end and the second end of the first tunable current source are an output end and an input end, respectively, and the one other end of the first tunable resistor and the one other end of the second tunable resistor are connected and then grounded.

12. The analog equalizer according to claim 8 , wherein when an output current of one of the first adjustable current and the second tunable current source increases, a bandwidth of the multi-stage equalization circuit becomes larger.

13. The analog equalizer according to claim 8 , wherein when a capacitance value of the third tunable capacitor increases, a frequency peak that the multi-stage equalization circuit is capable of compensating becomes larger.

14. The analog equalizer according to claim 8 , wherein the analog multiplexer comprises a fourth tunable resistor, a fifth tunable resistor and a plurality of input modules; the input modules respectively correspond to a plurality of stages of the multi-stage equalization circuit; each of the input modules comprises a fifth NMOS transistor, a sixth NMOS transistor and a fifth tunable current source; the fifth NMOS transistor and the sixth NMOS transistor have respective gates receive the corresponding differential output signal outputted from the multi-stage equalization circuit; the fifth NMOS transistor and the sixth NMOS transistor have respective drains output an equalized high-speed signal; the fifth NMOS transistor has a drain connected to one end of the fourth tunable resist

Assignees

• Mstar Semiconductor Inc

Inventors

• Sun Kai
• Lee Jiunn-Yih
• Lu wen-cai

Classifications

• H04L7/0012

  by comparing receiver clock with transmitter clock · CPC title

• H04L25/03273

  with carrier recovery circuitry · CPC title

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04B3/14

  characterised by the equalising network used · CPC title