Optimized data converter design using mixed semiconductor technology for cellular communications

Patent metadata

Field	Value
Publication number	US-9780942-B2
Application number	US-201514744303-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Jun 20, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A cellular radio architecture for a vehicle that includes a receiver module having a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals. Portions of the receiver and transmitter modules are fabricated with indium phosphide (InP) technologies and portions of the receiver and transmitter modules are fabricated with CMOS technologies.

First claim

What is claimed is:

1. A transceiver front-end circuit for a cellular radio, said transceiver circuit comprising:
an antenna structure operable to transmit signals and receive signals;
a multiplexer coupled to the antenna structure and including multiple signal paths, each signal path including a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals;
a receiver module including a separate signal channel for each of the signal paths in the multiplexer, each signal channel in the receiver module including a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal, wherein portions of receiver module are fabricated with indium phosphide (InP) technologies and portions of the receiver module are fabricated with CMOS technologies; and
a transmitter module including a transmitter delta-sigma modulator for converting digital data bits to the transmit signals, said transmitter module including a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer, wherein portions of transmitter module are fabricated with InP technologies and portions of the transmitter module are fabricated with CMOS technologies.

2. The transceiver circuit according to claim 1 wherein components and devices that operate at higher frequencies employ the InP technologies and components and devices that operate at lower frequencies and employ the CMOS technologies.

3. The transceiver circuit according to claim 1 wherein at least some of the InP and CMOS technologies in the receiver module are integrated using a micro-bump integration fabrication process and at least some of the InP and CMOS technologies in the transmitter module are integrated using a micro-bump integration fabrication process.

4. The transceiver circuit according to claim 1 wherein the InP technologies include InP double heterojunction bipolar transistor (DHBT) technologies.

5. The transceiver circuit according to claim 1 wherein each receiver delta-sigma modulator includes a combiner, a low noise amplifier (LNA), an LC filter and a quantizer circuit, said combiner receiving the receive signals from the circulator and a feedback signal from the quantizer circuit and providing an error signal to the LNA to provide an amplified error signal, said amplifier error signal being provided to the LC filter to provide a filtered error signal, and the filtered error signal being provided to the quantizer circuit, wherein the combiner, the LNA and portions of the LC filter are fabricated with InP technologies and portions of the LC filter are fabricated with CMOS technologies.

6. The transceiver circuit according to claim 5 wherein an inductor circuit in the LC filter is fabricated with InP technologies and a capacitor circuit in the LC circuit is fabricated with CMOS technologies.

7. The transceiver circuit according to claim 5 wherein the LC filter is a sixth-order filter.

8. The transceiver circuit according to claim 7 wherein the LC filter includes a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

9. The transceiver circuit according to claim 8 wherein each LC circuit includes an inductor and a capacitor array where the capacitor array includes a plurality of capacitors controlled by switches that provide coarse and fine tuning.

10. The transceiver circuit according to claim 5 wherein the LC filter includes a low-speed digital-to-analog converter (DAC) array that receives coefficient control bits to control the integrator circuits.

11. The transceiver circuit according to claim 1 wherein the transmitter module further includes a data weighted averaging (DWA) circuit that receives the transmit signals from the transmitter delta-sigma modulator and a digital-to-analog converter (DAC) that receives the transmit signals from the DWA circuit, wherein the DAC is fabricated in InP HBT technologies.

12. The transceiver circuit according to claim 11 wherein the DWA circuit modulates the digital thermal codes to shape out voltage and timing mismatch through DAC weighting elements, and wherein the DAC is a 4-bit DAC.

13. The transceiver circuit according to claim 11 wherein the transmitter delta-sigma modulator includes a dynamic element matching (DEM) circuit that employs an interleaving DEM algorithm.

14. The transceiver circuit according to claim 13 wherein a separate DEM circuit is provided for each bit of the DAC.

15. The transmitter circuit according to claim 1 wherein the power amplifier is fabricated in indium phosphide (InP) heterojunction bipolar transistor (HBT) and gallium nitride (GaN) high electron mobility transistor (HEMT) technologies.

16. A transceiver front-end circuit for a cellular radio, said transceiver circuit comprising:
an antenna structure operable to transmit signals and receive signals;
a multiplexer coupled to the antenna structure and including multiple signal paths, each signal path including a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals;
a receiver module including a separate signal channel for each of the signal paths in the multiplexer, each signal channel in the receiver module including a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal, wherein portions of the receiver module are fabricated with indium phosphide (InP) technologies and portions of the receiver module are fabricated with CMOS technologies, and wherein each receiver delta-sigma modulator includes a combiner, a low noise amplifier (LNA), an LC filter and a quantizer circuit, said combiner receiving the receive signals and a feedback signal from the quantizer circuit and providing an error signal to the LNA to provide an amplified error signal, said amplifier error signal being provided to the LC filter to provide a filtered error signal, and the filtered error signal being provided to the quantizer circuit, wherein the combiner, the LNA and portions of the LC filter are fabricated with InP technologies and portions of the LC filter are fabricated with CMOS technologies; and
a transmitter module including a transmitter delta-sigma modulator for converting digital data bits to the transmit signals, said transmitter module including a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer, wherein portions of transmitter module are fabricated with InP technologies and portions of the transmitter module are fabricated with CMOS technologies.

17. The transceiver circuit according to claim 16 wherein components and devices that operate at higher frequencies employ the InP technologies and components and devices that operate at lower frequencies and employ the CMOS technologies.

18. The transceiver circuit according to claim 16 wherein at least some of the InP and CMOS technologies in the receiver module are integrated using a micro-bump integration fabrication process and at least some of the InP and CMOS technologies in the transmitter module are integrated using a micro-bump integration fabrication process.

19. A transceiver front-end ci

Assignees

• Gm Global Tech Operations Llc

Inventors

• Talty Timothy J
• Baringer Cynthia D
• Ahmed Mohiuddin
• Cosand Albert E
• Li James Chingwei
• Petre Peter
• Xu Zhiwei A
• Kuan Yen-Cheng

Classifications

• H04L5/001

  the frequencies being arranged in component carriers · CPC title

• H04L5/0023

  Time-frequency-space · CPC title

• H04L5/1461 Primary

  Suppression of signals in the return path, i.e. bidirectional control circuits · CPC title

• H04B1/001

  Channel filtering, i.e. selecting a frequency channel within the SDR system (multiplexing of multicarrier modulation signals being represented by different frequencies H04L5/06; multiplexing of multicarrier modulation signals H04L5/023) · CPC title