Source-synchronous receiver using edge-detection clock recovery

Patent metadata

Field	Value
Publication number	US-9780795-B2
Application number	US-201415021874-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Sep 16, 2013
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

First claim

What is claimed is:

1. A receiver circuit, comprising:
a first sampler circuit to resolve a data signal in response to a first timing reference signal received from a phase-alignment circuit;
a second sampler circuit to resolve a timing reference signal in response to a second timing reference signal from the phase-alignment circuit and to output a phase indicator; and,
the phase-alignment circuit to produce, based on the timing reference signal and the phase indicator, the first timing reference signal and the second timing reference signal.

2. The receiver circuit of claim 1 , wherein the phase-alignment circuit is to produce a first phase adjusted signal to be used as the first timing reference signal and the second timing reference signal.

3. The receiver circuit of claim 1 , wherein, based on the phase indicator, the phase-alignment circuit is to adjust the first phase adjusted signal to minimize a phase error between the timing reference signal and the second timing reference signal minus the setup time of the second sampler.

4. The receiver circuit of claim 1 , wherein the phase-alignment circuit comprises:
a loop filter to receive the phase indicator and to control a first phase adjuster, the first phase adjuster producing the first phase adjusted signal.

5. The receiver circuit of claim 4 , further comprising:
a second phase adjuster, the second phase adjuster to produce a second phase adjusted signal that has an approximately constant delay between the first phase adjusted signal and the second phase adjusted signal, the second phase adjusted signal to be used as the first timing reference signal.

6. The receiver circuit of claim 4 , wherein the first phase adjuster comprises a first digitally controlled phase mixer and the second phase adjuster comprises a second digitally controlled phase mixer, the first digitally controlled phase mixer receiving a first digital input value, the second digitally controlled phase mixer receiving a second digital input value that is a predetermined offset from the first digital input value.

7. The receiver circuit of claim 6 , wherein the predetermined offset is obtained from a lookup table that is based on the first digital input value.

8. A timing reference receiver circuit for a source-synchronous data communication system, comprising:
a phase detector to receive a reference signal and a feedback signal; and,
a phase-alignment circuit to receive the reference signal and an output of the phase detector, the phase-alignment circuit to generate a phase adjusted signal and the feedback signal based on the reference signal, the phase adjusted signal to be provided to a timing reference input of a data sampler circuit of the source-synchronous data communication system.

9. The timing reference receiver circuit of claim 8 , wherein the phase detector comprises:
a timing reference sampler circuit to resolve the reference signal in response to the feedback signal and to output a phase indicator, the design of data sampler circuit and the design of the timing reference sampler circuit being matched for approximately equal timing characteristics.

10. The timing reference receiver of claim 8 , wherein, based on the output of the phase detector, the phase-alignment circuit is to adjust the feedback signal to minimize a phase error between the reference signal and the feedback signal minus an offset of the phase detector.

11. The timing reference receiver of claim 8 , wherein a delay between the reference signal and the phase adjusted signal is based on the output of the phase detector.

12. The timing reference receiver of claim 8 , wherein the phase-alignment circuit comprises:
a phase feedback path that adjusts a first digital input value to a first phase delay element to minimize a phase error between the reference signal and the feedback signal minus an offset of the phase detector.

13. The timing reference receiver of claim 12 , wherein a second phase delay element generates the phase adjusted signal, the second phase delay element receiving a second digital input value that is based on the first digital input value.

14. The timing reference receiver of claim 13 , wherein the second digital input value is calculated from the first digital input value to produce a selected delay between the feedback signal and the phase adjusted signal.

15. The timing reference receiver of claim 8 , wherein the phase-alignment circuit comprises an injection locked oscillator.

16. A method of generating a data sampling timing reference, comprising:
receiving a data signal to be sampled based on a source-synchronous timing reference signal;
receiving the source-synchronous timing reference signal;
sampling the source-synchronous timing reference signal with a first sampler based on a first phase-adjusted timing reference signal to produce a phase error indicator;
sampling the data signal with a second sampler based on a second phase-adjusted timing reference signal;
based on the phase error indicator, controlling a first phase adjuster input value to align the phase of the first phase-adjusted timing reference signal such that a phase difference between the source-synchronous timing reference signal and the first phase-adjusted timing reference signal minus the setup time of the first sampler is minimized; and,
based on the phase adjuster input value, controlling a second phase adjuster input value to produce the second phase-adjusted timing reference signal, the second phase-adjusted timing reference signal controlled to have a selected delay between the first phase-adjusted timing reference signal and the second phase-adjusted timing reference signal.

17. The method of claim 16 , wherein the second phase adjuster input value is a predetermined offset based on the first phase adjuster input value.

18. The method of claim 16 , wherein the design of the first sampler and the design of the second sampler are matched for approximately equal timing characteristics.

19. The method of claim 16 , further comprising:
filtering the phase error indicator to produce the first phase adjuster input value.

20. The method of claim 16 , further comprising:
providing the second phase-adjusted timing reference signal to sample a plurality of data signals with a respective plurality of samplers.

Assignees

• Rambus Inc

Inventors

• Navid Reza

Classifications

• H04B1/22

  for receivers in which no local oscillation is generated · CPC title

• H03L7/0812 Primary

  and where no voltage or current controlled oscillator is used · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• H04B1/7085

  using a code tracking loop, e.g. a delay-locked loop · CPC title

• H03L7/24

  using a reference signal directly applied to the generator · CPC title