Clock generating circuit and semiconductor apparatus including the same

Patent metadata

Field	Value
Publication number	US-9780767-B2
Application number	US-201615152708-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	Feb 5, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal. The second clock generator may generate a multi-phase clock signal from a second clock signal. The common mode generator may generate a reference voltage based on the first and second clock signals.

First claim

What is claimed is:

1. A clock generation circuit comprising:
a first clock generator configured to receive a first clock signal through a first input node and to output first and second output clock signals;
a second clock generator configured to receive a second clock signal, which has a phase lagging behind the first clocks signal by 180 degrees, through a second input node, and to output third and fourth output clock signals; and
a common mode generator, to which the first clock signal and second clock signal are input, configured to generate a reference voltage and provide the reference voltage to the first and second clock generators.

2. The clock generation circuit of claim 1 , wherein the first clock generator comprises:
a first multi-phase clock generator configured to generate the first output clock signal by delaying the first clock signal by a first amount of time; and
a second multi-phase clock generator configured to generate the second output clock signal by delaying the first clock signal CLK by a second amount of time.

3. The clock generation circuit of claim 2 , wherein the first multi-phase clock generator comprises:
a first resistive element coupled between the first input node and a first output node; and
a capacitive element coupled between the first output node and a ground voltage node,
wherein the first output clock signal is output through the first output node.

4. The clock generation circuit of claim 2 , wherein the second multi-phase clock generator comprises:
a second capacitive element coupled between the first input node and a second output node; and
a second resistive element coupled between the second output node and the common mode generator,
wherein the second output clock signal is output through the second output node.

5. The clock generation circuit of claim 1 , wherein the second clock generator comprises:
a third multi-phase clock generator configured to generate the third output clock signal by delaying the second clock signal by a first amount of time; and
a fourth multi-phase clock generator configured to generate the fourth output clock signal by delaying the second clock signal by a second amount of time.

6. The clock generation circuit of claim 5 , wherein the third multi-phase clock generator comprises:
a third resistive element coupled between the second input node and a third output node; and
a third capacitive element coupled between the third output node and a ground voltage node,
wherein the third output clock signal is output through the third output node.

7. The clock generation circuit of claim 5 , wherein the fourth multi-phase clock generator comprises:
a fourth capacitive element coupled between the second input node and a fourth output node; and
a fourth resistive element coupled between the fourth output node and the common mode generator,
wherein the fourth output clock signal is output through the fourth output node.

8. The clock generation circuit of claim 1 , wherein the common mode generator comprises:
a fifth resistive element coupled between the first input node and a common node; and
a sixth resistive element coupled between the second input node and the common node,
wherein the common mode generator provides the reference voltage to the first and second clock generators through the common node.

9. The clock generation circuit of claim 8 , wherein the first and second clock generators are coupled to the common node and receive the reference voltage through the common node.

10. A clock generation circuit comprising:
a first multi-phase clock generator coupled to a first input node through which a first clock is provided, the first multi-phase clock generator generating a first output clock signal;
a second multi-phase clock generator coupled between the first input node and a common node, the second multi-phase clock generator generating a second output clock signal;
a third multi-phase clock generator coupled to a second input node through which a second clock signal is provided, the third multi-phase clock generator generating a third output clock signal;
a fourth multi-phase clock generator coupled between the second input node and the common node, the fourth multi-phase clock generator generating a fourth output clock signal; and
a common mode generator coupled between the first input node and the second input node, the common mode generator providing the common node with a reference voltage.

11. The clock generation circuit of claim 10 , wherein the first and second clock signals have a phase difference of 180 degrees.

12. The clock generation circuit of claim 10 , wherein the first multi-phase clock generator comprises:
a first resistive element coupled between the first input node and a first output node; and
a capacitive element coupled between the first output node and a ground voltage node,
wherein the first output clock signal is output through the first output node.

13. The clock generation circuit of claim 10 , wherein the second multi-phase clock generator comprises:
a second capacitive element coupled between the first input node and a second output node; and
a second resistive element coupled between the second output node and the common node,
wherein the second output clock signal is output through the second output node.

14. The clock generation circuit of claim 10 , wherein the third multi-phase clock generator comprises:
a third resistive element coupled between the second input node and a third output node; and
a third capacitive element coupled between the third output node and a ground voltage node,
wherein the third output clock signal is output through the third output node.

15. The clock generation circuit of claim 10 , wherein the fourth multi-phase clock generator comprises:
a fourth capacitive element coupled between the second input node and a fourth output node; and
a fourth resistive element coupled between the fourth output node and the common node,
wherein the fourth output clock signal is output through the fourth output node.

16. The clock generation circuit of claim 10 , wherein the common mode generator comprises:
a fifth resistive element coupled between the first input node and a common node; and
a sixth resistive element coupled between the second input node and the common node.

17. A semiconductor apparatus comprising:
a clock generation circuit including first and second clock generators and a common mode generator, the first clock generator receiving a first clock signal through a first input node and outputting first and second output clock signals, the second clock generator receiving a second clock signal, which has a phase lagging behind the first clocks signal by 180 degrees, through a second input node and outputting third and fourth output clock signals, the common mode generator, to which the first clock signal and second clock signal are input, generating a reference voltage and providing the reference voltage to the first and second clock generators; and
a data sampler configured to receive data signals in synchronization with the first to fourth output clock signals generated by the clock generation circuit.

18. The semiconductor apparatus of claim 17 , further comprising a deserializer configured to generate internal data signals in response to output signals of the data sampler.

19. The semiconductor apparatus of claim 17 , further comprising a filter configured to detect whether the data signals have been precisely sampled by the data sampler.

Assignees

• Sk Hynix Inc

Inventors

• Park Myeong Jae

Classifications

• H03K5/1506 Primary

  with parallel driven output stages; with synchronously driven series connected output stages · CPC title