Double balanced mixer

Patent metadata

Field	Value
Publication number	US-9780728-B1
Application number	US-201615083939-A
Country	US
Kind code	B1
Filing date	Mar 29, 2016
Priority date	Mar 29, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A FET based double balanced mixer (DBM) that exhibits good conversion gain and IIP3 values and provides improved linearity and wide bandwidth. In one embodiment, a first balun is configured to receive a local oscillator (LO) signal and generate two balanced LO signals that are coupled to two corresponding opposing nodes of a four-node FET ring. A second balun is configured to pass an RF signal on the unbalanced side. The FET ring includes at least four FETs connected as branches of a ring, with the source of each FET connected to the drain of a next FET in the ring. Each FET is preferably fabricated as, or configured as, a low threshold voltage device having its gate connected to its drain, which causes the FET to operate as a diode, but with the unique characteristic of having close to a zero turn-on voltage.

First claim

What is claimed is:

1. A double balanced mixer having a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side and having a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side, the double balanced mixer including:
(a) a four-node ring including four branches, each branch including at least one field effect transistor (FET), each FET having a source, a drain, and a gate, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and the gate and the drain of each FET are connected together as a diode, wherein a first pair of opposing nodes of the four-node FET ring are connected to the pair of ports on the balanced side of the first balun, and a second pair of opposing nodes of the four-node FET ring are connected through corresponding capacitors to the pair of ports on the balanced side of the second balun; and
(b) an intermediate frequency (IF) signal port coupled through corresponding quarter-wave isolation elements to the second pair of opposing nodes of the four-node FET ring.

2. The invention of claim 1 , wherein the FETs are low threshold voltage FETs.

3. The invention of claim 1 , wherein the quarter-wave isolation elements are quarter-wave transmission lines.

4. The invention of claim 1 , wherein the four-node FET ring includes at least two FETs per branch.

5. The invention of claim 1 , wherein the four-node FET ring includes at least four FETs per branch.

6. The invention of claim 1 , wherein the double balanced mixer is fabricated as an integrated circuit.

7. The invention of claim 6 , wherein the integrated circuit is fabricated on a silicon-on-insulator (SOI) or a silicon-on-sapphire (SOS) substrate.

8. The invention of claim 7 , wherein the integrated circuit is fabricated using one of thin film, partially depleted, or fully depleted CMOS technology.

9. A double balanced mixer, including:
(a) a four-node field effect transistor (FET) ring including four branches, each branch including at least one FET having a source, a drain, and a gate, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and the gate and the drain of each FET are connected together as a diode having close to a zero turn-on voltage;
(b) a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side coupled to a corresponding pair of first opposing nodes of the four-node FET ring;
(c) a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side coupled through corresponding capacitors to a corresponding pair of second opposing nodes of the four-node FET ring; and
(d) an intermediate frequency (IF) signal port coupled through corresponding quarter-wave isolation elements to the second opposing nodes of the four-node FET ring.

10. The invention of claim 9 , wherein the FETs are low threshold voltage FETs.

11. The invention of claim 9 , wherein the quarter-wave isolation elements are quarter-wave transmission lines.

12. The invention of claim 9 , wherein the four-node FET ring includes at least two FETs per branch.

13. The invention of claim 9 , wherein the four-node FET ring includes at least four FETs per branch.

14. The invention of claim 9 , wherein the double balanced mixer is fabricated as an integrated circuit.

15. The invention of claim 14 , wherein the integrated circuit is fabricated on a silicon-on-insulator (SOI) or a silicon-on-sapphire (SOS) substrate.

16. The invention of claim 15 , wherein the integrated circuit is fabricated using one of thin film, partially depleted, or fully depleted CMOS technology.

17. A method for fabricating a double balanced mixer having a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side and having a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side, including:
(a) providing a four-node field effect transistor (FET) ring including four branches, each branch including at least one FET, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and each FET has a gate and a drain connected together as a diode having close to a zero turn-on voltage, wherein a first pair of opposing nodes of the four-node FET ring are connected to the pair of ports on the balanced side of the first balun, and a second pair of opposing nodes of the four-node FET ring are connected through corresponding capacitors to the pair of ports on the balanced side of the second balun; and
(b) providing an intermediate frequency (IF) signal port coupled through corresponding quarter-wave isolation elements to the second pair of opposing nodes of the four-node FET ring.

18. The method of claim 17 , wherein the FETs are low threshold voltage FETs.

19. The method of claim 17 , wherein the quarter-wave isolation elements are quarter-wave transmission lines.

20. The invention of claim 17 , wherein the four-node FET ring includes at least two FETs per branch.

21. The invention of claim 17 , wherein the four-node FET ring includes at least four FETs per branch.

22. The method of claim 17 , further including fabricating the double balanced mixer as an integrated circuit.

23. The method of claim 22 , further including fabricating the integrated circuit on a silicon-on-insulator (SOI) or a silicon-on-sapphire (SOS) substrate.

24. The method of claim 23 , further including fabricating the integrated circuit using one of thin film, partially depleted, or fully depleted CMOS technology.

25. A method for fabricating a double balanced mixer, including:
(a) providing a four-node field effect transistor (FET) ring including four branches, each branch including at least one FET having a source, a drain, and a gate;
(b) configuring the source of each FET to be connected to the drain of a next FET in the four-node FET ring;
(c) configuring each FET as a diode having close to a zero turn-on voltage by connecting the drain of such FET to the gate of such FET;
(d) providing a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side coupled to a corresponding pair of first opposing nodes of the four-node FET ring;
(e) providing a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side coupled through corresponding capacitors to a corresponding pair of second opposing nodes of the four-node FET ring; and
(f) providing an intermediate frequency (IF) signal port coupled through corresponding quarter-wave isolation elements to the second opposing nodes of the four-node FET ring.

26. The method of claim 25 , wherein the FETs are low threshold voltage FETs.

27. The method of claim 25 , wherein the quarter-wave isolation elements are quarter-wave transmission lines.

28. The method of claim 25 , wherein the four-node FET ring includes at least two FETs per branch.

29. The method of claim 25 , wherein the four-node FET ring includes at least four FETs per branch.

30. The me

Assignees

• Peregrine Semiconductor Corp

Inventors

• Salameh Daoud

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H01L29/786

  Electricity · mapped topic

• H03D7/02

  by means of diodes (H03D7/14 - H03D7/22 take precedence) · CPC title

• H01L27/1203

  Electricity · mapped topic

• H03H7/42

  Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns · CPC title