Semiconductor structure with oxide semiconductor layer

Patent metadata

Field	Value
Publication number	US-9780230-B2
Application number	US-201615368647-A
Country	US
Kind code	B2
Filing date	Dec 4, 2016
Priority date	Aug 26, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a patterned oxide semiconductor layer disposed on a base;
two source/drain regions disposed on the patterned oxide semiconductor layer, wherein the two source/drain regions are separated by a recess, and each source/drain region respectively comprises an inner sidewall facing the recess and an outer sidewall disposed opposite to the inner sidewall;
a protective layer disposed on a sidewall of the patterned oxide semiconductor layer, being not disposed on the inner sidewall of the source/drain region;
a gate layer disposed on the patterned oxide semiconductor layer; and
a gate dielectric layer disposed between the gate layer and the patterned oxide semiconductor layer.

2. The semiconductor structure according to claim 1 , wherein the protective layer directly contacts the sidewall of the patterned oxide semiconductor layer.

3. The semiconductor structure according to claim 1 , wherein the protective layer is further disposed on the outer sidewall of the source/drain region and a top surface of the source/drain region.

4. The semiconductor structure according to claim 3 , wherein the protective layer has a sidewall vertically aligned with the inner sidewall of the source/drain region.

5. The semiconductor structure according to claim 1 , wherein the protective layer is disposed only on the sidewall of the patterned oxide semiconductor layer.

6. The semiconductor structure according to claim 1 , wherein the protective layer is disposed only on the sidewall of the patterned oxide semiconductor layer and the outer sidewall of the source/drain region.

7. The semiconductor structure according to claim 1 , wherein the protective layer comprises a high-k dielectric material.

8. The semiconductor structure according to claim 1 , wherein the patterned oxide semiconductor layer comprises a first patterned oxide semiconductor layer and a second patterned oxide semiconductor layer.

9. The semiconductor structure according to claim 1 , further comprising a second oxide semiconductor layer disposed between the gate dielectric layer and the patterned oxide semiconductor layer.

10. The semiconductor structure according to claim 1 , further comprising:
a first dielectric layer disposed on the base;
a first patterned conductive layer disposed in the first dielectric layer and corresponding to the gate layer; and
a second dielectric layer disposed in the first dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Fu
• Wu Chun-Yuan

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic