Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9780170-B2
Application number	US-201615204364-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Aug 4, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a memory cell, and
a control unit that performs a write operation and an erase operation to the memory cell,
the memory cell comprising: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode,
the oxide semiconductor layer including a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer,
wherein the control unit, during the erase operation, provides a higher voltage to the oxide semiconductor layer than to the gate electrode.

2. The semiconductor memory device according to claim 1 , further comprising
a plurality of the memory cells,
wherein the charge accumulation layer is disposed straddling the plurality of memory cells.

3. The semiconductor memory device according to claim 1 , wherein
the oxide semiconductor layer includes the stacked structure in which the n type oxide semiconductor layer and the p type oxide semiconductor layer are provided in this order from the charge accumulation layer side.

4. The semiconductor memory device according to claim 1 , wherein
the oxide semiconductor layer includes the stacked structure in which the p type oxide semiconductor layer and the n type oxide semiconductor layer are provided in this order from the charge accumulation layer side.

5. The semiconductor memory device according to claim 1 , wherein
the n type oxide semiconductor layer includes indium, gallium, zinc, and oxygen, and
the p type oxide semiconductor layer includes: at least one of copper and tin; and oxygen.

6. A semiconductor memory device, comprising:
a memory cell,
the memory cell comprising: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode,
the oxide semiconductor layer including a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer, wherein
disposed in part of the oxide semiconductor layer is a contact layer including at least one of indium zinc oxide, indium tin oxide, titanium, molybdenum, gold, gallium zinc oxide, aluminum, zinc oxide, platinum, nickel, and tin.

7. The semiconductor memory device according to claim 6 , wherein
the n type oxide semiconductor layer includes indium, gallium, zinc, and oxygen,
the p type oxide semiconductor layer includes copper and oxygen, and
the contact layer includes at least one of indium zinc oxide and gold.

8. The semiconductor memory device according to claim 6 , wherein
the n type oxide semiconductor layer includes indium, gallium, zinc, and oxygen,
the p type oxide semiconductor layer includes tin and oxygen, and
the contact layer includes at least one of indium tin oxide, titanium, aluminum, and gold.

9. A semiconductor memory device, comprising:
a memory cell,
the memory cell comprising: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode,
the oxide semiconductor layer including a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer, wherein
the semiconductor memory device further
comprises a substrate, and
includes a structure in which the oxide semiconductor layer is disposed above the substrate, the charge accumulation layer is disposed above the oxide semiconductor layer, and the gate electrode is disposed above the charge accumulation layer.

10. The semiconductor memory device according to claim 9 , further comprising
a plurality of the memory cells,
wherein the charge accumulation layer is disposed straddling the plurality of memory cells.

11. The semiconductor memory device according to claim 9 , wherein
the oxide semiconductor layer includes the stacked structure in which the n type oxide semiconductor layer and the p type oxide semiconductor layer are provided in this order from the charge accumulation layer side.

12. The semiconductor memory device according to claim 9 , wherein
the oxide semiconductor layer includes the stacked structure in which the p type oxide semiconductor layer and the n type oxide semiconductor layer are provided in this order from the charge accumulation layer side.

13. The semiconductor memory device according to claim 9 , wherein
the n type oxide semiconductor layer includes indium, gallium, zinc, and oxygen, and
the p type oxide semiconductor layer includes: at least one of copper and tin; and oxygen.

14. A semiconductor memory device, comprising:
a plurality of memory cells,
the plurality of memory cells comprising:
a plurality of conductive layers that are stacked;
a charge accumulation layer having a first surface and a second surface opposite to the first surface, the second surface disposed facing side surfaces of the plurality of conductive layers; and
an oxide semiconductor layer disposed facing the first surface of the charge accumulation layer,
the oxide semiconductor layer including a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

15. The semiconductor memory device according to claim 14 , wherein
the oxide semiconductor layer extends in a direction that the conductive layers are stacked, and one of the n type oxide semiconductor layer and the p type oxide semiconductor layer surrounds a periphery of the other.

16. The semiconductor memory device according to claim 14 , further comprising
a control unit that performs a write operation and an erase operation to the plurality of memory cells,
wherein the control unit, during the erase operation, provides a higher voltage to the oxide semiconductor layer than to the plurality of conductive layers.

17. The semiconductor memory device according to claim 14 , wherein
the charge accumulation layer is disposed straddling the plurality of memory cells.

18. The semiconductor memory device according to claim 14 , wherein
the oxide semiconductor layer includes the stacked structure in which the n type oxide semiconductor layer and the p type oxide semiconductor layer are provided in this order from the charge accumulation layer side.

19. The semiconductor memory device according to claim 14 , wherein
the oxide semiconductor layer includes the stacked structure in which the p type oxide semiconductor layer and the n type oxide semiconductor layer are provided in this order from the charge accumulation layer side.

20. The semiconductor memory device according to claim 14 , wherein
the n type oxide semiconductor layer includes indium, gallium, zinc, and oxygen and
the p type oxide semiconductor layer includes: at least one of copper and tin; and oxygen.

21. The semiconductor memory device according to claim 14 , wherein
disposed in part of the oxide semiconductor layer is a contact layer including at least one of indium zinc oxide, indium tin oxide, titanium, molybdenum, gold, gallium zinc oxide, aluminum, zinc oxide, platinum, nickel, and tin.

22. The semiconductor memory device according to claim 21 , wherein
the n type oxide semiconductor layer includes indium, gallium, zinc, and oxygen,
the p type oxide semiconductor layer includes copper and oxygen, and
the contact layer includes at least one of indium zinc oxide and gold.

23. The semiconductor memory device according to claim 21 , wherein

Assignees

• Toshiba Memory Corp

Inventors

• Ota Kensuke
• Irisawa Toshifumi
• Kawai Tomoya
• Matsushita Daisuke
• Tezuka Tsutomu

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11573

  Electricity · mapped topic

• G11C16/10

  Programming or data input circuits · CPC title

• H01L29/24

  Electricity · mapped topic