Transistor substrate and display device

Patent metadata

Field	Value
Publication number	US-9780125-B2
Application number	US-201615346810-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Dec 2, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A transistor substrate includes a plurality of first transistors formed between a power supply wire and a first conductive wire, and a plurality of second transistors formed between the power supply wire and a second conductive wire. A length of a portion of the power supply wire between the plurality of second transistors and a drive signal generation circuit is longer than a length of a portion of the power supply wire between the plurality of first transistors and the drive signal generation circuit, and a total sum of channel widths of second channels included in the plurality of second transistors is wider than a total sum of channel widths of first channels included in the plurality of first transistors.

First claim

What is claimed is:

1. A transistor substrate which has a display region in which a pixel is formed and a peripheral region positioned outside the display region, the transistor substrate comprising:
a common wire formed in the peripheral region;
a control circuit connected to one end of the common wire;
a first conductive wire and a second conductive wire which are formed to be spaced apart from the common wire;
a plurality of first transistors formed between the common wire and the first conductive wire; and
a plurality of second transistors formed between the common wire and the second conductive wire,
wherein each of the plurality of first transistors includes:
a first gate electrode;
a first A electrode and a first B electrode which are formed on both sides of the first gate electrode to sandwich the first gate electrode; and
a first channel facing the first gate electrode,

wherein each of the plurality of second transistors includes:
a second gate electrode;
a second A electrode and a second B electrode which are formed on both sides of the second gate electrode to sandwich the second gate electrode; and
a second channel facing the second gate electrode,

wherein the first A electrode is connected to the first conductive wire, and the first B electrode is connected to the common wire, in each of the plurality of first transistors,
wherein the second A electrode is connected to the second conductive wire, and the second B electrode is connected to the common wire, in each of the plurality of second transistors,
wherein a length of a portion of the common wire between the plurality of second transistors and the control circuit is longer than a length of a portion of the common wire between the plurality of first transistors and the control circuit, and
wherein a total sum of channel widths of the second channels included in the plurality of second transistors is wider than a total sum of channel widths of the first channels included in the plurality of first transistors.

2. The transistor substrate according to claim 1 ,
wherein, when a direction intersecting an extending direction of the common wire is set to a width direction,
an area of a portion of the common wire which faces a region in which the plurality of second transistors are formed in the width direction is smaller than an area of a portion of the common wire which faces a region in which the plurality of first transistors are formed in the width direction.

3. The transistor substrate according to claim 2 , further comprising:
a third conductive wire formed to be spaced apart from the common wire; and
a plurality of third transistors formed between the common wire and the third conductive wire,
wherein each of the plurality of third transistors includes:
a third gate electrode;
a third A electrode and a third B electrode which are formed on both sides of the third gate electrode to sandwich the third gate electrode; and
a third channel facing the third gate electrode,

wherein the third A electrode is connected to the third conductive wire, and the third B electrode is connected to the common wire, in each of the plurality of third transistors,
wherein a length of a portion of the common wire between the plurality of third transistors and the control circuit is longer than the length of the portion of the common wire between the plurality of second transistors and the control circuit, and
wherein a total sum of channel widths of the third channels included in the plurality of third transistors is wider than the total sum of the channel widths of the second channels included in the plurality of second transistors.

4. The transistor substrate according to claim 2 ,
wherein, when a direction intersecting an extending direction of the common wire is set to a width direction,
the plurality of second transistors are arrayed in the extending direction and the width direction.

5. The transistor substrate according to claim 2 , further comprising:
a plurality of first transistor groups which are formed between the common wire and the first conductive wire and are connected to each other in parallel; and
a plurality of second transistor groups which are formed between the common wire and the second conductive wire and are connected to each other in parallel,
wherein, when a direction intersecting an extending direction of the common wire is set to a width direction,
the plurality of first transistor groups are arrayed in the extending direction,
wherein the plurality of second transistor groups are arrayed in the extending direction,
wherein each of the plurality of first transistor groups includes the plurality of first transistors arrayed in the width direction,
wherein each of the plurality of second transistor groups includes the plurality of second transistors arrayed in the width direction, and
wherein a length of a portion of the common wire between the plurality of second transistor groups and the control circuit is longer than a length of a portion of the common wire between the plurality of first transistor groups and the control circuit.

6. The transistor substrate according to claim 2 , further comprising:
a first common electrode and a second common electrode which are formed in the display region,
wherein the first common electrode serves also as a first detection electrode which detects proximity or contact of an object,
wherein the second common electrode serves also as a second detection electrode which detects proximity or contact of the object,
wherein the first common electrode is electrically connected to the first conductive wire, and
wherein the second common electrode is electrically connected to the second conductive wire.

7. The transistor substrate according to claim 1 , further comprising:
a third conductive wire formed to be spaced apart from the common wire; and
a plurality of third transistors formed between the common wire and the third conductive wire,
wherein each of the plurality of third transistors includes:
a third gate electrode;
a third A electrode and a third B electrode which are formed on both sides of the third gate electrode to sandwich the third gate electrode; and
a third channel facing the third gate electrode,

wherein the third A electrode is connected to the third conductive wire, and the third B electrode is connected to the common wire, in each of the plurality of third transistors,
wherein a length of a portion of the common wire between the plurality of third transistors and the control circuit is longer than the length of the portion of the common wire between the plurality of second transistors and the control circuit, and
wherein a total sum of channel widths of the third channels included in the plurality of third transistors is wider than the total sum of the channel widths of the second channels included in the plurality of second transistors.

8. The transistor substrate according to claim 7 ,
wherein, when a direction intersecting an extending direction of the common wire is set to a width direction,
an area of a portion of the common wire which faces a region in which the plurality of second transistors are formed in the width direction is smaller than an area of a portion of the common wire which faces a region in which the plurality of first transistors are formed in the width direction, and
wherein an area of a portion of the common wire which faces a region in which the plurality of third transistors are formed in the width direction is smaller than the area of the portion of the common wire which faces the region in which the plurality of second transistors are formed in the width direction.

9. The transistor substrate according to

Assignees

• Japan Display Inc

Inventors

• Koide Gen

Classifications

• G02F2201/121

  common or background · CPC title

• G06F3/044

  by capacitive means · CPC title

• G02F2201/123

  pixel · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/134336

  Matrix · CPC title