Interconnection structure and manufacturing method thereof

US9780025B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9780025-B2
Application numberUS-201514850848-A
CountryUS
Kind codeB2
Filing dateSep 10, 2015
Priority dateDec 30, 2014
Publication dateOct 3, 2017
Grant dateOct 3, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an opening to at least partially expose the first conductor. The second dielectric layer is disposed on the etch stop layer and has at least one hole therein. The hole of the second dielectric layer is in communication with the opening of the etch stop layer. The second conductor is disposed at least partially in the hole of the second dielectric layer and is electrically connected to the first conductor through the opening of the etch stop layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing an interconnection structure, the method comprising: forming a first hole and a second hole in a first dielectric layer; forming a first conductor and a second conductor in the first hole and the second hole respectively; etching back the first dielectric layer, such that each of the first conductor and the second conductor has a portion protruding from the first dielectric layer; forming an etch stop layer on the first dielectric layer, the protruding portion of the first conductor, and the protruding portion of the second conductor, wherein the etch stop layer has a raised portion covering the protruding portion of the second conductor, the raised portion has a cap part covering a top surface of the protruding portion of the second conductor and at least one spacer part disposed on at least one sidewall of the protruding portion of the second conductor, and the spacer part of the raised portion is thicker than the cap part of the raised portion; forming a second dielectric layer on the etch stop layer; etching at least one third hole in the second dielectric layer and the etch stop layer, such that the protruding portion of the first conductor is at least partially exposed by the third hole, wherein the etching the third hole is stopped before reaching the first dielectric layer, and the raised portion of the etch stop layer remains on the protruding portion of the second conductor after the etching; and forming a third conductor in the third hole. 2. The method of claim 1 , wherein the etching the third hole comprises: etching a top hole in the second dielectric layer; and etching an opening in the etch stop layer, such that the protruding portion of the first conductor is at least partially exposed by the opening, wherein the opening and the top hole are in communication with each other to form the third hole. 3. The method of claim 2 , wherein the etch stop layer has higher etch resistance to an etchant used to etch the top hole in the second dielectric layer than that of the second dielectric layer. 4. The method of claim 2 , wherein the etch stop layer has higher etch resistance to an etchant used to etch the top hole in the second dielectric layer than that of the first dielectric layer. 5. An interconnection structure, comprising: a first dielectric layer having at least one hole therein; a first conductor disposed at least partially in the hole of the first dielectric layer; an etch stop layer disposed on the first dielectric layer, the etch stop layer having an opening to at least partially expose the first conductor, wherein the first dielectric layer has a top surface facing the etch stop layer; a second dielectric layer disposed on the etch stop layer and having at least one hole therein, wherein the hole of the second dielectric layer is in communication with the opening of the etch stop layer; a second conductor disposed at least partially in the hole of the second dielectric layer and electrically connected to the first conductor through the opening of the etch stop layer, wherein the etch stop layer has a first portion between the second conductor and the first dielectric layer, and the first conductor is surrounded by the first portion of the etch stop layer; and a third conductor disposed partially in the first dielectric layer, wherein the third conductor has a portion protruding from the top surface of the first dielectric layer, the etch stop layer has a raised portion covering the protruding portion of the third conductor, the raised portion has a cap part covering a top surface of the protruding portion of the third conductor and at least one spacer part disposed on at least one sidewall of the protruding portion of the third conductor, and the spacer part is thicker than the cap part. 6. The interconnection structure of claim 5 , wherein the etch stop layer and the second dielectric layer have different etch resistance properties. 7. The interconnection structure of claim 5 , wherein the etch stop layer and the first dielectric layer have different etch resistance properties. 8. The interconnection structure of claim 5 , wherein the etch stop layer is made of a carbon-rich material. 9. The interconnection structure of claim 5 , wherein the first conductor has a portion protruding from the top surface of the first dielectric layer. 10. The interconnection structure of claim 5 , wherein the etch stop layer has a second portion disposed between the first dielectric layer and the second dielectric layer, and the first portion is thinner than the second portion. 11. The interconnection structure of claim 5 , further comprising: a barrier layer having a portion between the second conductor and the etch stop layer. 12. The interconnection structure of claim 5 , further comprising: a barrier layer having a portion over and in contact with the etch stop layer. 13. An interconnection structure, comprising: a first dielectric layer; at least one first conductor disposed at least partially in the first dielectric layer; a second dielectric layer having a hole therein; a third dielectric layer disposed between the first dielectric layer and the second dielectric layer, the third dielectric layer having an opening in communication with the hole of the second dielectric layer, wherein the first conductor is at least partially exposed by the opening of the third dielectric layer, and the third dielectric layer has higher etch resistance to an etchant used to etch the hole of the second dielectric layer than that of the second dielectric layer; a second conductor electrically connected to the first conductor through the hole of the second dielectric layer and the opening of the third dielectric layer; and a third conductor disposed partially in the first dielectric layer and having a portion protruding from the first dielectric layer, wherein the third dielectric layer has a raised portion covering the protruding portion of the third conductor, the raised portion has a cap part covering a top surface of the protruding portion of the third conductor and at least one spacer part disposed on at least one sidewall of the protruding portion of the third conductor, and the spacer part is thicker than the cap part. 14. The interconnection structure of claim 13 , wherein the third dielectric layer has higher etch resistance to the etchant used to etch the hole of the second dielectric layer than that of the first dielectric layer. 15. The interconnection structure of claim 13 , wherein the third dielectric layer is made of a carbon-rich material. 16. The interconnection structure of claim 13 , wherein the first conductor has a portion protruding from the first dielectric layer. 17. The interconnection structure of claim 16 , further comprising: a barrier layer having a portion on at least one sidewall of the protruding portion of the first conductor. 18. The interconnection structure of claim 13 , wherein the first dielectric layer is not exposed by the opening of the third dielectric layer. 19. The interconnection structure of claim 13 , wherein the third dielectric layer has a first portion between the second conductor and the first dielectric layer. 20. The interconnection structure of claim 19 , wherein the third dielectric layer has a second portion between the first dielectric layer and the second dielectric layer, and the second portion is thicker than the first portion.

Assignees

Inventors

Classifications

  • by forming conductive members before forming protective insulating material · CPC title

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • H10W20/081Primary

    by forming openings in the dielectric parts · CPC title

  • on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

  • H10W20/056Primary

    by filling conductive material into holes, grooves or trenches · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9780025B2 cover?
An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an o…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/081. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).