Array substrate, display device, and manufacturing method of array substrate

Patent metadata

Field	Value
Publication number	US-9779949-B2
Application number	US-201414428863-A
Country	US
Kind code	B2
Filing date	May 28, 2014
Priority date	Jan 24, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

An array substrate is provided, wherein a pixel electrode has the same material as a source/drain and has a thickness less than that of the source/drain, or a common electrode has the same material as a gate and has a thickness less than that of the gate, which guarantees transmittance of the array substrate while reducing the process complexity. A display device and a manufacturing method of the array substrate are also provided.

First claim

The invention claimed is:

1. An array substrate including a gate, a common electrode, source/drain and a pixel electrode, wherein the gate and the common electrode are disposed in a same layer or the source/drain and the pixel electrode are disposed in a same layer,
wherein an entirety of the gate and an entirety of the common electrode are disposed in the same layer, the entirety of the common electrode and the entirety of the gate are made of a same electrode material and a total thickness of the common electrode is less than that of the gate, the common electrode is formed with a plurality of slits, and the common electrode has a transmittance greater than 30%; and
wherein an entirety of the source/drain and an entirety of the pixel electrode are disposed in the same layer, the entirety of the pixel electrode and the entirety of the source/drain are made of a same electrode material and a total thickness of the pixel electrode is less than that of the source/drain, the pixel electrode is formed with a plurality of slits, and the pixel electrode has a transmittance greater than 30%.

2. The array substrate of claim 1 , wherein the electrode material is a single-layer metal film or a multi-layer composite film of Al, Cu, Mo, AlNd, Cr, Ti, Ag, or a composite film with a metal/medium one-dimension photonic crystal structure.

3. The array substrate of claim 2 , wherein the electrode material is a single-layer metal film of Ag, the gate has a thickness of 2000 Å and the common electrode has a thickness of 50 Å.

4. The array substrate of claim 2 , wherein the electrode material is a composite film comprising ZnS, Ag, ZnS, and Ag, wherein ZnS, Ag, ZnS, and Ag are disposed in sequence in a direction from the substrate to the composite film, the common electrode or the pixel electrode comprises only a composite layer of ZnS, Ag, and ZnS, and ZnS, Ag, ZnS, and Ag have thicknesses of 400 Å,180 Å, 400 Å , and 2000 Å, respectively.

5. The array substrate of wherein the common electrode or the pixel electrode has a thickness of 10˜100 Å and a transmittance of 30%˜90%.

6. The array substrate of claim 1 , wherein each of the common electrode and the pixel electrode is formed with a plurality of slits, and
slits in the common electrode and slits in the pixel electrode are parallel to each other.

7. The array substrate of claim 6 , wherein projections of slits in the common electrode on the substrate and projections of slits in the pixel electrode on the substrate do not overlap.

8. The array substrate of claim 2 , wherein the common electrode or the pixel electrode has a thickness of 10˜100 Å and a transmittance of 30%˜90%.

9. The array substrate of claim 3 , wherein the common electrode or the pixel electrode has a thickness of 10˜100 Å and a transmittance of 30%˜90%.

10. The array substrate of claim 4 , wherein the common electrode or the pixel electrode has a thickness of 10˜100 Å and a transmittance of 30%˜90%.

11. The array substrate of claim 2 , wherein each of the common electrode and the pixel electrode is formed with a plurality of slits, and
slits in the common electrode and slits in the pixel electrode are parallel to each other.

12. The array substrate of claim 3 , wherein each of the common electrode and the pixel electrode is formed with a plurality of slits, and
slits in the common electrode and slits in the pixel electrode are parallel to each other.

13. The array substrate of claim 4 , wherein each of the common electrode and the pixel electrode is formed with a plurality of slits, and
slits in the common electrode and slits in the pixel electrode are parallel to each other.

14. The array substrate of claim 5 , wherein each of the common electrode and the pixel electrode is formed with a plurality of slits, and
slits in the common electrode and slits in the pixel electrode are parallel to each other.

15. The array substrate of claim 11 , wherein projections of slits in the common electrode on the substrate and projections of slits in the pixel electrode on the substrate do not overlap.

16. The array substrate of claim 12 , wherein projections of slits in the common electrode on the substrate and projections of slits in the pixel electrode on the substrate do not overlap.

17. The array substrate of claim 13 , wherein projections of slits in the common electrode on the substrate and projections of slits in the pixel electrode on the substrate do not overlap.

18. The array substrate of claim 14 , wherein projections of slits in the common electrode on the substrate and projections of slits in the pixel electrode on the substrate do not overlap.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Feng
• Cao Zhanfeng
• Yao Qi
• Gu Jingxia

Classifications

• H10P14/40 Primary

  of conductive or resistive materials · CPC title

• H01L29/45

  Electricity · mapped topic

• G02F2001/134372

  Physics · mapped topic

• H01L21/283 Primary

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic