Alarm output circuit

Patent metadata

Field	Value
Publication number	US-9779608-B2
Application number	US-201514853961-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Jul 5, 2013
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

An alarm output circuit can cope with simultaneous generations of a plurality of alarm factors based on alarm signals output from one output terminal. The alarm output circuit notifies externally of generations of alarm factors in an intelligent power module. A digital/analog converter, into which digital data indicating the presences and absences of generations of the alarm factors is input, outputs corresponding voltages. A voltage control oscillator outputs a signal of a frequency corresponding to an output voltage of the digital/analog converter.

First claim

What is claimed is:

1. An alarm output circuit into which presences and absences of generations of a plurality of alarm factors in an intelligent power module are input as logical values, and which, based on the logical values, notifies externally of the generations of the alarm factors, the alarm output circuit comprising:
a digital/analog converter into which an item of digital data configured of a logical value relating to one or more of each of the alarm factors is input, and which outputs a voltage corresponding to the item of digital data; and
a voltage control oscillator which outputs a signal of a frequency corresponding to the output voltage of the digital/analog converter.

2. The alarm output circuit according to claim 1 , further including:
a latch timer which is activated when one of the alarm factors is generated; and
a circuit which inputs a logical product of the output signal of the voltage control oscillator and a signal indicating that the latch timer is in operation.

3. The alarm output circuit according to claim 2 , further including:
a sample/hold circuit which, in accordance with a sample/hold signal, passes or holds the output voltage of the digital/analog converter, wherein
the voltage control oscillator outputs a signal of a frequency corresponding to the output voltage of the sample/hold circuit.

4. The alarm output circuit according to claim 3 , wherein
a logical product of the signal which indicates that the latch timer is in operation, and a signal which selects an input or non-input of the sample/hold signal into the sample/hold circuit, is used as the sample/hold signal for the sample/hold circuit.

5. The alarm output circuit according to claim 1 , further including:
a sample/hold circuit which, in accordance with a sample/hold signal, passes or holds the output voltage of the digital/analog converter, wherein
the voltage control oscillator outputs a signal of a frequency corresponding to the output voltage of the sample/hold circuit.

6. The alarm output circuit according to claim 5 , wherein
a logical product of a signal which indicates that the latch timer is in operation, and a signal which selects an input or non-input of the sample/hold signal into the sample/hold circuit, is used as the sample/hold signal for the sample/hold circuit.

7. A logic device, comprising:
a digital-to-analog converter configured to receive a plurality of inputs respectively corresponding to alarm signals, and in response to one or a combination of the alarm signals being generated, to output a voltage level corresponding to the one or the combination of generated alarm signals; and
a frequency generator configured to output a frequency corresponding to the voltage level.

8. The logic device of claim 7 , further comprising:
a timing device configured to receive the plurality of inputs respectively corresponding to alarm signals, and to output a timing signal indicating whether at least one alarm signal has been generated; and
an output logic device configured to receive the timing signal and the frequency corresponding to the voltage level, and to output the frequency corresponding to the voltage level if the timing signal indicates that at least one alarm signal has been generated.

9. The logic device of claim 8 , further comprising:
a sample-and-hold device configured to receive the voltage level corresponding to the one or the combination of generated alarm signals from the digital-to-analog converter and to output the voltage level to the frequency generator; and
a mode selection device configured to receive the timing signal and a mode selection signal, and to output the mode selection signal to the sample-and-hold device if the timing signal indicates that at least one alarm signal has been generated;
wherein the sample-and-hold device is further configured to, in response to the mode selection signal, output to the frequency generator a voltage level that corresponds to an alarm signal initially generated until the timing signal indicates that no alarm signal has been generated.

10. The logic device of claim 8 , wherein the timing device includes an OR gate configured to receive the plurality of inputs respectively corresponding to alarm signals, and a latch timer configured to receive an output of the OR gate.

11. The logic device of claim 7 , wherein the frequency generator includes a voltage-controlled oscillator.

Assignees

• Fuji Electric Co Ltd

Inventors

• Minoya Yoshiaki

Classifications

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H04L25/00

  Baseband systems · CPC title

• G08B21/18 Primary

  Status alarms (G08B21/02 takes precedence) · CPC title

• H03K17/18 Primary

  Modifications for indicating state of switch · CPC title