Multi-line image processing with parallel processing units

Patent metadata

Field	Value
Publication number	US-9779470-B2
Application number	US-201715409848-A
Country	US
Kind code	B2
Filing date	Jan 19, 2017
Priority date	Jul 18, 2013
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. The multiple outputs of the multi-line processing block are coupled to corresponding multiple inputs of a subsequent multi-line processing block in the image processing system.

First claim

The invention claimed is:

1. An image processing pipeline comprising:
a first multi-line processing block configured to apply multi-line processing to a plurality of pixel values; and
a second multi-line processing block configured to apply multi-line processing to the plurality of pixel values which have been processed by the first multi-line processing block,
wherein no line store module is implemented between the first and second multi-line processing blocks in the image processing pipeline.

2. The image processing pipeline of claim 1 wherein the first multi-line processing block comprises a plurality of processing units configured to apply the multi-line processing to respective pixel values.

3. The image processing pipeline of claim 2 wherein the processing units of the first multi-line processing block are configured to output processed pixel values directly to inputs of the second multi-line processing block.

4. The image processing pipeline of claim 1 wherein the first multi-line processing block comprises a plurality of inputs configured to receive pixel values relating to a plurality of pixel lines of an image in parallel.

5. The image processing pipeline of claim 4 wherein a number of processing units of the first multi-line processing block is equal to the number of inputs of the first processing block.

6. The image processing pipeline of claim 4 wherein a number of processing units of the first multi-line processing block is less than the number of inputs of the first processing block.

7. The image processing pipeline of claim 1 further comprising a line store module implemented before the first multi-line processing block in the image processing pipeline, wherein the line store module is configured to:
store pixel values of pixel lines of an image; and
provide pixel values in parallel to inputs of the first multi-line processing block.

8. The image processing pipeline of claim 1 further comprising a further multi-line processing block configured to provide pixel values in parallel to inputs of the first multi-line processing block.

9. The image processing pipeline of claim 1 wherein the multi-line processing which the first processing block is configured to apply is asymmetric filtering.

10. The image processing pipeline of claim 9 wherein the asymmetric filtering is bilateral filtering.

11. The image processing pipeline of claim 1 wherein the multi-line processing which the first processing block is configured to apply is symmetric filtering.

12. The image processing pipeline of claim 1 further comprising one or more single-line processing blocks configured to process N pixel values in parallel, wherein the second multi-line processing block is arranged to provide N outputs for further processing by one or more of the one or more single-line processing blocks, where N is greater than one.

13. The image processing pipeline of claim 1 further comprising at least one further multi-line processing block arranged either: (i) to provide pixel values in parallel to the first multi-line processing block, or (ii) to receive, in parallel, pixel values processed by the second multi-line processing block.

14. The image processing pipeline of claim 1 wherein the first multi-line processing block has multiple outputs which are provided as multiple inputs for the second multi-line processing block.

15. The image processing pipeline of claim 1 wherein the multi-line processing which the first multi-line processing block is configured to apply is different to the multi-line processing which the second multi-line processing block is configured to apply.

16. A method of processing an image in an image processing pipeline, the method comprising:
applying multi-line processing to a plurality of pixel values at a first multi-line processing block of the image processing pipeline;
receiving, at a second multi-line processing block of the image processing pipeline, the plurality of pixel values which have been processed by the first multi-line processing block and which have not been stored in a line store module subsequent to being processed by the first multi-line processing block; and
applying, multi-line processing to the received the plurality of pixel values at the second multi-line processing block.

17. The method of claim 16 further comprising outputting processed pixel values from the second multi-line processing block.

18. The method of claim 17 further comprising applying further processing to the pixel values outputted from the second multi-line processing block.

19. The method of claim 16 wherein the second processing block provides N outputs for further processing by one or more single-line processing blocks, where N is greater than one, the method further comprising processing the N outputs in parallel by the one or more single-line processing blocks.

20. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed/executed by a processor, causes a system to generate an image processing pipeline, said image processing pipeline comprising:
a first multi-line processing block configured to apply multi-line processing to a plurality of pixel values; and
a second multi-line processing block configured to apply multi-line processing to the plurality of pixel values which have been processed by the first multi-line processing block,
wherein no line store module is implemented between the first and second multi-line processing blocks in the image processing pipeline.

Assignees

• Imagination Tech Ltd

Inventors

• Bishop Michael
• Taylor Morgyn

Classifications

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N23/80

  Camera processing pipelines; Components thereof · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• H04N5/23229

  Electricity · mapped topic

• G06T2207/20021

  Dividing image into blocks, subimages or windows · CPC title