Enabling poll/select style interfaces with coherent accelerators

US9779041B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9779041-B2
Application numberUS-201614987258-A
CountryUS
Kind codeB2
Filing dateJan 4, 2016
Priority dateNov 10, 2015
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an operating system receives, from an application, a system call to attach a hardware context with the coherent accelerator block or character device. The operating system generates a channel based on a file descriptor associated with the attach system call. The operating system associates the channel with a hardware context selected from a plurality of hardware contexts available to the coherent accelerator, wherein the hardware context is attached to the application. Upon receiving, from the application, a system call to check for exceptions that have occurred on the coherent accelerator block device or character device, the operating system returns an indication of any exceptions which have occurred while the coherent accelerator was using the hardware context to the application.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for checking for exceptions on a coherent accelerator, the method comprising: receiving, from an application, a system call to attach a hardware context with the coherent accelerator, wherein the coherent accelerator is either a block device or a character device; generating a channel based on a file descriptor associated with the attach system call; upon attaching the hardware context to the application, associating the generated channel with the hardware context selected from a plurality of hardware contexts available to the coherent accelerator; and upon receiving, from the application, a system call to check for exceptions that have occurred on the coherent accelerator: identifying the hardware context that is attached to the application from the plurality of hardware contexts, based on the generated channel; and returning an indication of any exceptions which have occurred while the coherent accelerator was executing instructions under the hardware context to the application. 2. The method of claim 1 , wherein generating the channel based on the file descriptor comprises: identifying a file pointer address associated with the file descriptor; performing a shift operation on the file pointer address; and using the shifted file pointer address as the generated channel. 3. The method of claim 2 , wherein performing the shift operation on the file pointer address comprises shifting the file pointer address to the right by eight bits, and truncating the shifted file pointer address to a lower 32 bits. 4. The method of claim 1 , wherein generating the channel based on the file descriptor comprises generating and truncating a hash value based on a file pointer address associated with the file descriptor. 5. The method of claim 1 , wherein associating the generated channel with the hardware context comprises: intercepting the hardware context from the application when the application requests to attach to the hardware context; and saving the generated channel into the intercepted hardware context. 6. The method of claim 1 , wherein returning the indication of any exceptions comprises: notifying at least one of the application or a device driver of the exceptions from the hardware context via a notification service, wherein the notification service uses the generated channel associated with the hardware context to identify the arriving exceptions, and wherein identifying the exceptions comprises searching the hardware context for an interrupt source number associated with an interrupt generated due to at least one of a page fault, error, or I/O event. 7. The method of claim 1 , further comprising: upon identifying the exceptions that have occurred on the coherent accelerator, packaging the exceptions into an exception structure that corresponds to the hardware context, wherein the exception structure comprises information associated with the identified exceptions; and storing the exception structure. 8. The method of claim 7 , further comprising: after returning, to the application, an indication that an exception has occurred while the coherent accelerator was running with the hardware context, receiving, from the application, a system call to identify the exceptions for the hardware context; identifying the exception structure for the hardware context, based on the generated channel; and returning the exception structure to the application. 9. The method of claim 1 , wherein the system call to check for exceptions that have occurred on the coherent accelerator is either a poll subroutine or select subroutine.

Assignees

Inventors

Classifications

  • Single storage device · CPC title

  • using page tables, e.g. page table structures · CPC title

  • Monitoring storage devices or systems · CPC title

  • using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

  • G06F13/22Primary

    using successive scanning, e.g. polling (G06F13/24 takes precedence) · CPC title

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Frequently asked questions

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What does patent US9779041B2 cover?
Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an operating system receives, from an application, a system call to attach a hardware context with the coherent accelerator block or character device. The operating system generates a channel based on a file descriptor associated with the atta…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F13/22. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).