Managing translation invalidation

Patent metadata

Field	Value
Publication number	US-9779028-B1
Application number	US-201615088302-A
Country	US
Kind code	B1
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).

First claim

What is claimed is:

1. A processor, comprising:
one or more processing elements, including at least a first processing element that includes one or more VA-indexed structures indexed by virtual addresses and that is configured to handle invalidation messages, the handling including:
in response to determining that a first invalidation message applies to a subset of virtual addresses consisting of fewer than all virtual addresses associated with a first set of one or more translation context values, searching the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address in the subset and invalidating any entries that are found;
in response to determining that a second invalidation message applies to all virtual addresses associated with a second set of one or more translation context values and that no entry exists in one or more invalidation-tracking structures corresponding to the second set of one or more translation context values, bypassing searching of any of the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address associated with the second set of one or more translation context values, where the one or more invalidation-tracking structures track invalidation of different sets of one or more translation context values; and
in response to determining that a third invalidation message applies to all virtual addresses associated with a third set of one or more translation context values and that at least one entry exists in the one or more invalidation-tracking structures corresponding to the third set of one or more translation context values, storing invalidation information in the one or more invalidation-tracking structures to invalidate the third set of one or more translation context values and delaying searching of any of the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address associated with the third set of one or more translation context values.

2. The processor of claim 1 , wherein the one or more invalidation-tracking structures includes entries that map a plurality of sets of one or more translation context values to corresponding translation context identifiers, where a total number of bits used to represent all possible translation context identifiers is smaller than a total number of bits used to represent all possible sets of one or more translation context values.

3. The processor of claim 2 , wherein the VA-indexed structures include entries that store at least a portion of a virtual addresses and a corresponding translation context identifier associated with that virtual address.

4. The processor of claim 2 , wherein handling the first invalidation message includes: accessing the one or more invalidation-tracking structures to determine a translation context identifier corresponding to the first set of one or more translation context values, and preserving any invalidation information indicating that the first set of one or more translation context values remain valid after handling the first invalidation message.

5. The processor of claim 1 , wherein the one or more invalidation-tracking structures include a first invalidation-tracking structure that includes entries for a plurality of translation context values representing a first type of translation context information, and a second invalidation-tracking structure that includes entries for a plurality of translation context values representing a second type of translation context information.

6. The processor of claim 1 , wherein the one or more processing elements includes a plurality of processing elements, and the first invalidation message, the second invalidation message, and the third invalidation message are all received by the first processing element and are all sent by a processing element different from the first processing element.

7. The processor of claim 1 , wherein searching of any of the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address associated with any set of one or more translation context values causes an interruption to a pipeline of the first processing element.

8. The processor of claim 7 , wherein the bypassing causes the second invalidation message to be handled without interrupting the pipeline of the first processing element.

9. The processor of claim 7 , wherein the delaying causes the third invalidation message to be handled without interrupting the pipeline of the first processing element at least until the one or more invalidation-tracking structures are flushed.

10. The processor of claim 1 , wherein the VA-indexed structures include at least one of the following structures: a translation lookaside buffer, a level one data cache, a level one instruction cache, or a page table walker.

11. A method for managing translation invalidation in a processor, the method comprising:
handling an invalidation message in at least a first processing element, of one or more processing elements of the processor, that includes one or more VA-indexed structures indexed by virtual addresses, the handling including:
in response to determining that a first invalidation message applies to a subset of virtual addresses consisting of fewer than all virtual addresses associated with a first set of one or more translation context values, searching the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address in the subset and invalidating any entries that are found;
in response to determining that a second invalidation message applies to all virtual addresses associated with a second set of one or more translation context values and that no entry exists in one or more invalidation-tracking structures corresponding to the second set of one or more translation context values, bypassing searching of any of the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address associated with the second set of one or more translation context values, where the one or more invalidation-tracking structures track invalidation of different sets of one or more translation context values; and
in response to determining that a third invalidation message applies to all virtual addresses associated with a third set of one or more translation context values and that at least one entry exists in the one or more invalidation-tracking structures corresponding to the third set of one or more translation context values, storing invalidation information in the one or more invalidation-tracking structures to invalidate the third set of one or more translation context values and delaying searching of any of the VA-indexed structures in the first processing element to find any entries that correspond to a virtual address associated with the third set of one or more translation context values.

12. The method of claim 11 , wherein the one or more invalidation-tracking structures includes entries that map a plurality of sets of one or more translation context values to corresponding translation context identifiers, where a total number of bits used to represent all possible translation context identifiers is smaller than a total number of bits used to represent all possible sets of one or more translation context values.

13. The method of claim 12 , wherein the VA-indexed structures include entries that store at least a portion of a virtual addresses and a corresponding translation context identifier associated with that virtual address.

14. The method of claim 12 , wh

Assignees

• Cavium Inc

Inventors

• Mukherjee Shubhendu Sekhar
• Bertone Mike

Classifications

• G06F2212/683

  Invalidation · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F2212/1016

  Performance improvement · CPC title