PCIE device power state control

Patent metadata

Field	Value
Publication number	US-9778720-B2
Application number	US-201113976545-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.

First claim

What is claimed is:

1. A method, the method comprising:
receiving, by a chipset, an indication of an idle state capability of a device connected to a platform, a power state of the platform being controlled by the chipset;
determining, by the chipset, an idle power state compatible with the device, the determining of the idle power state compatible with the device being based, at least in part, on a latency of the device and the received indication of the idle state capability of the device;
directing, by the chipset, the device to enter the determined idle power state;
transitioning, the device, to the determined idle power state based on, in part, a power state of the chipset as reported from the chipset; and
exiting the platform, by the chipset, from an idle state prior to the device exiting the determined idle power state.

2. The method of claim 1 , wherein the indication of an idle state capability of the platform connected device includes information regarding at least one idle state and a corresponding latency and a power consumption associated therewith.

3. The method of claim 1 , wherein the received information is stored for a future reference by the chipset.

4. The method of claim 1 , wherein information indicative of the latency is received from the device.

5. The method of claim 1 , wherein the determining of the idle power state compatible with the device is based, at least in part, on a state of the chipset.

6. The method of claim 1 , further comprising receiving an indication of at least one platform parameter value and further determining the idle power state compatible with the device based, at least in part, on the at least one received platform parameter value.

7. A non-transitory medium having processor-executable instructions stored thereon, the medium comprising:
instructions to receive, by a chipset, an indication of an idle state capability of a device connected to a platform;
instructions to determine an idle power state compatible with the device, the determining of the idle power state compatible with the device being based, at least in part, on a latency of the device and the received indication of the idle state capability of the device;
instructions to direct the device to enter the determined idle power state;
instructions to transition the device to the determined idle power state based on, in part, a power state of the chipset as reported from the chipset; and
instructions to exit the platform from an idle state prior to the device exiting the determined idle power state.

8. The medium of claim 7 , wherein the indication of an idle state capability of the platform connected device includes information regarding at least one idle state and a corresponding latency and a power consumption associated therewith.

9. The medium of claim 7 , wherein the received information is stored for a future reference by the chipset.

10. The medium of claim 7 , wherein information indicative of the latency is received from the device.

11. The medium of claim 7 , wherein the determining of the idle power state compatible with the device is based, at least in part, on a state of the chipset.

12. The medium of claim 7 , further comprising:
instructions to receive an indication of at least one platform parameter value; and
instructions to determine the idle power state compatible with the device based, at least in part, on the at least one received platform parameter value.

Assignees

• Kumar Anil K
• Crawford John H
• Diefenbaugh Paul S
• Intel Corp

Inventors

• Kumar Anil K
• Crawford John H
• Diefenbaugh Paul S

Classifications

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F11/3051

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/325

  Power saving in peripheral device · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title