Multiple digital data sequences from an arbitrary data generator of a printhead assembly

Patent metadata

Field	Value
Publication number	US-9776399-B2
Application number	US-201415308055-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

In an example, a piezoelectric printhead assembly includes a micro-electro mechanical system (MEMS) die including a plurality of nozzles. An application-specific integrated circuit (ASIC) die is coupled to the MEMS die by a plurality of wire bonds, wherein each of the wire bonds corresponds to a respective nozzle of the plurality of nozzles. An arbitrary data generator (ADG) on the ASIC is to provide a digital data sequence, and a phase selector is to enable multiple data read operations of the ADG to generate multiple delayed digital data sequences.

First claim

What is claimed is:

1. A piezoelectric printhead assembly comprising:
a micro-electro mechanical system (MEMS) die including a plurality of nozzles;
an application-specific integrated circuit (ASIC) die coupled to the MEMS die by a plurality of wire bonds, wherein each of the wire bonds corresponds to a respective nozzle of the plurality of nozzles;
an arbitrary data generator (ADG) on the ASIC to provide a digital data sequence; and
a phase selector to enable multiple data read operations of the ADG to generate multiple delayed digital data sequences.

2. A piezoelectric printhead assembly as in claim 1 , further comprising:
multiple storage registers, each register corresponding with a respective delayed digital data sequence to store a digital data step of the respective delayed digital data sequence.

3. A piezoelectric printhead assembly as in claim 2 , wherein each digital data step of a delayed digital data sequence comprises an 8 bit digital number representing a digital voltage level.

4. A piezoelectric printhead assembly as in claim 3 , further comprising:
a digital-to-analog converter (DAC) associated with each nozzle, each DAC to receive a respective 8 bit digital number from a respective storage register and to convert the respective 8 bit digital number to an analog voltage.

5. A piezoelectric printhead assembly as in claim 4 , further comprising:
a first clock to drive the phase selector at a first frequency such that each data read operation acquires and stores a single digital data step of a delayed digital data sequence in a respective storage register at the first frequency; and
a second clock running at a second frequency to drive multiple digital data steps from the storage registers into respective DACs simultaneously at a second frequency.

6. A piezoelectric printhead assembly as in claim 5 , wherein the first frequency is a multiple of the second frequency, the multiple being equal to the number of multiple delayed digital data sequences.

7. A piezoelectric printhead assembly as in claim 4 , further comprising:
a driver amplifier associated with each nozzle to receive an analog voltage from a DAC and to condition the analog voltage into a portion of a nozzle-drive waveform.

8. A piezoelectric printhead assembly comprising:
a micro-electro mechanical system (MEMS) die including a plurality of nozzles;
a first and a second application-specific integrated circuit (ASIC) coupled to the MEMS die by respective first and second pluralities of wire bonds, wherein each of the first plurality of wire bonds corresponds to a respective nozzle of a first number of the plurality of nozzles and each of the second plurality of wire bonds corresponds to a respective nozzle of a second number of the plurality of nozzles; and,
on each ASIC:
a plurality of arbitrary data generators (ADGs), each ADG to provide a digital data sequence;
an ADG selector to select a digital data sequence of a selected ADG; and
a phase selector to enable the construction of multiple delayed digital data sequences from the selected ADG.

9. A piezoelectric printhead assembly as in claim 8 , further comprising:
a first and second plurality of power amplifiers on the first and second ASIC, respectively, each power amplifier corresponding with a particular nozzle, and each power amplifier to amplify one of the multiple delayed digital data sequences into a nozzle-drive waveform capable of driving the particular nozzle.

10. A method of driving nozzles on a piezoelectric printhead assembly comprising:
selecting one of a plurality of arbitrary data generators (ADGs) to provide a digital data sequence; and
generating multiple temporally offset digital data sequences from the digital data sequence of the selected ADG.

11. A method as in claim 10 , wherein generating multiple temporally offset digital data sequences comprises:
for each temporally offset digital data sequence, reading digital data steps from the selected ADG at a first frequency; and
alternating reading of digital data steps between the multiple temporally offset digital data sequences at a second frequency.

12. A method as in claim 11 , wherein the second frequency is a multiple of the first frequency, and the multiple is equal to the number of multiple temporally offset digital data sequences.

13. A method as in claim 10 , further comprising:
conditioning the multiple temporally offset digital data sequences into corresponding multiple temporally offset nozzle-drive waveforms to drive print nozzles.

14. A method as in claim 13 , wherein conditioning the multiple temporally offset digital data sequences comprises:
converting each temporally offset digital data sequence into a temporally offset analog voltage sequence; and,
amplifying each temporally offset analog voltage sequence into a temporally offset nozzle-drive waveform.

15. A method as in claim 10 , wherein selecting one of a plurality of ADGs comprises selecting a first ADG on a first application-specific integrated circuit (ASIC), the method further comprises:
selecting a second ADG from a plurality of ADGs on a second ASIC to provide a second digital data sequence; and,
generating multiple temporally offset digital data sequences from the second digital data sequence of the second ADG.

Assignees

• Hewlett Packard Development Co Lp

Inventors

• Fricke Peter James
• Linn Scott A
• Molinari Luca

Classifications

• B41J2/04561

  detecting presence or properties of a drop in flight · CPC title

• B41J2/04581

  controlling heads based on piezoelectric elements · CPC title

• B41J2/04558 Primary

  detecting presence or properties of a dot on paper · CPC title

• B41J2/0459

  Height of the driving signal being adjusted · CPC title

• B41J2/04541 Primary

  Specific driving circuit · CPC title