Pin connector structure and method

US9775242B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9775242-B2
Application numberUS-201615005589-A
CountryUS
Kind codeB2
Filing dateJan 25, 2016
Priority dateJun 26, 2012
Publication dateSep 26, 2017
Grant dateSep 26, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.

First claim

Opening claim text (preview).

What is claimed is: 1. A pin grid array, comprising; a substrate, including a number of electrical connections; a matrix material forming an interface with the electrical connections on the substrate; and a number of pins including pin shafts, and having pin heads embedded in the matrix, wherein one or more pins includes a pin head having at least three legs extending at an angle with respect to the pin shaft between, but not including 0 and 90 degrees. 2. The pin grid array of claim 1 , wherein the pin head includes a textured top surface. 3. The pin grid array of claim 2 , wherein the textured top surface includes one or more channels. 4. The pin grid array of claim 1 , wherein the matrix material includes solder. 5. The pin grid array of claim 4 , wherein the solder includes a tin-antimony solder. 6. A method of forming a pin connection, comprising: forming a pin, including a pin head having at least three legs extending at an angle with respect to the pin shaft between, but not including 0 and 90 degrees; placing the pin head in contact with an electrical connection on a substrate surface; and flowing solder around the pin head and in contact with the electrical connection to embed the pin head. 7. The method of claim 6 , further including channeling gas bubbles from beneath the pin head using gaps formed by the at least three legs. 8. The method of claim 6 , further including forming one or more channels in the top surface. 9. The method of claim 6 , wherein the pin grid connection is formed as part of a pin grid array.

Assignees

Inventors

Classifications

  • Leads having protrusions, e.g. for retention or insert stop · CPC title

  • by bonding or embedding conductive wires or strips · CPC title

  • Pins or blades for co-operation with sockets · CPC title

  • Special cross-section of a lead; Different cross-sections of different leads; Matching cross-section, e.g. matched to a land · CPC title

  • Means for venting or for letting gases escape · CPC title

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Frequently asked questions

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What does patent US9775242B2 cover?
Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/11. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).