Image sensing device with analog-dithering scheme

Patent metadata

Field	Value
Publication number	US-9774809-B2
Application number	US-201514850663-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Apr 17, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

An image sensing device includes: a clock signal control block suitable for generating first and second clock control signals to have variable logic combinations for each unit row time; a frequency division block suitable for generating first and second clock signals having different phases based on a reference clock signal and controlling a first delay time reflected in the first clock signal and a second delay time reflected in the second clock signal for each unit row time based on the first and a second clock control signals; and a pixel signal processing block suitable for converting a pixel signal inputted for each unit row time into a digital signal based on the first and second clock signals.

First claim

What is claimed is:

1. An image sensing device, comprising:
a clock signal control block configured to generate first and second clock control signals to have variable logic combinations for each unit row time, wherein the clock signal control block generates the first and second clock control signals of irregular logic combinations;
a frequency division block configured to generate first and second clock signals having different phases based on a reference clock signal, and control a first delay time reflected in the first clock signal and a second delay time reflected in the second clock signal for each unit row time based on the first and second clock control signals; and
a pixel signal processing block configured to convert a pixel signal inputted for each unit row time into a digital signal based on the first and second clock signals,
wherein the digital signal generated by the pixel signal processing block is analog-dithered based on the first and second clock signals whose phases are controlled differently for each unit row time.

2. The image sensing device of claim 1 , wherein the frequency division block irregularly controls the first and second delay times.

3. The image sensing device of claim 1 , wherein the frequency division block includes:
a first division unit configured to divide the frequency of the reference clock signal by 2 to generate a first divided clock signal;
a first delay unit configured to delay the first divided clock signal by a predetermined delay time to generate a first delayed clock signal;
a first selection unit configured to select one of the first divided clock signal and the first delayed clock signal as the first clock signal based on the first clock control signal;
a second division unit configured to divide the frequency of an inverted signal of the reference clock signal by 2 to generate a second divided clock signal;
a second delay unit configured to delay the second divided clock signal by the predetermined delay time to generate a second delayed clock signal; and
a second selection unit configured to select one of the second divided clock signal and the second delayed clock signal as the second clock signal based on the second clock control signal.

4. The image sensing device of claim 3 , wherein the predetermined delay time is shorter than a quarter of a cycle of the reference clock signal.

5. The image sensing device of claim 1 , wherein the clock signal control block further generates a third clock control signal and a fourth clock control signal to have variable logic combinations for each unit row time, and
the frequency division block irregularly controls the first and second delay times for each unit row time based on the first to fourth clock control signals.

6. The image sensing device of claim 5 , wherein the frequency division block includes:
a first division unit configured to divide the frequency of the reference clock signal by 2 to generate a first divided clock signal;
a first delay unit configured to delay the first divided clock signal by a predetermined delay time to generate a first delayed clock signal;
a second delay unit configured to delay the first delayed clock signal by the predetermined delay time to generate a second delayed clock signal;
a third delay unit configured to delay the second delayed clock signal by the predetermined delay time to generate a third delayed clock signal;
a first selection unit configured to select one of the first divided clock signal and the first delayed clock signal as a first selection clock signal based on the first clock control signal;
a second selection unit configured to select one of the second delayed clock signal and the third delayed clock signal as a second selection clock signal based on the first clock control signal;
a third selection unit configured to select one of the first selection clock signal and the second selection clock signal as the first clock signal based on the third clock control signal;
a second division unit configured to divide the frequency of an inverted signal of the reference clock signal by 2 to generate a second divided clock signal;
a fourth delay unit configured to delay the second divided clock signal by the predetermined delay time to generate a fourth delayed clock signal;
a fifth delay unit configured to delay the fourth delayed clock signal by the predetermined delay time to generate a fifth delayed clock signal;
a sixth delay unit configured to delay the fifth delayed clock signal by the predetermined delay time to generate a sixth delayed clock signal;
a fourth selection unit configured to select one of the second divided clock signal and the fourth delayed clock signal as a third selection clock signal based on the second clock control signal;
a fifth selection unit configured to select one of the fifth delayed clock signal and the sixth delayed clock signal as a fourth selection clock signal based on the second clock control signal; and
a sixth selection unit configured to select one of the third selection clock signal and the fourth selection clock signal as the second clock signal based on the fourth clock control signal.

7. The image sensing device of claim 6 , wherein the predetermined delay time is shorter than a quarter of a cycle of the reference clock signal.

8. An image sensing device, comprising:
a pixel array configured to output a pixel signal by rows for each unit row time;
a ramp voltage generation block configured to generate a ramp voltage having a predetermined ramp up/down pattern for each unit row time, wherein the ramp voltage generation block generates the ramp voltage increasing or dropping by a predetermined voltage for each unit row time; and
a pixel signal processing block configured to convert the pixel signal into a digital signal based on first and second divided clock signals, wherein the digital signal is analog-dithered based on the first and second divided clock signals whose phases are differently controlled for each unit row time.

9. The image sensing device of claim 8 , further comprising:
a clock signal control block configured to generate first and second clock control signals to have variable logic combinations for each unit row time, wherein the clock signal control block generates the first and second clock control signals of irregular logic combinations; and
a frequency division block configured to generate the first and second divided clock signals with different phases based on a reference clock signal and control a first delay time reflected in the first clock signal and a second delay time reflected in the second clock signal for each unit row time based on the first and second clock control signals.

10. The image sensing device of claim 9 , wherein
the frequency division block irregularly controls the first and second delay time.

11. The image sensing device of claim 9 , wherein the frequency division block includes:
a first division unit configured to divide the frequency of the reference clock signal by 2 to generate a first divided clock signal;
a first delay unit configured to delay the first divided clock signal by a predetermined delay time to generate a first delayed clock signal;
a first selection unit configured to select one of the first divided clock signal and the first delayed clock signal as the first clock signal based on the first clock control signal;
a second division unit configured to divide the frequency of an inverted signal of the reference clock signal by 2 to generate a second divided clock signal;
a second delay unit configured to delay the second divided clock signal by the predetermined delay time to generate a second delayed cloc

Assignees

• Sk Hynix Inc

Inventors

• Song Jung-Eun

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N5/378

  Electricity · mapped topic

• H04N5/3765 Primary

  Electricity · mapped topic

• H04N5/3745

  Electricity · mapped topic

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title